block1.tan.rpt

用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[3]           ; c24:inst10|count[4]           ; clk5       ; clk5     ; None                        ; None                      ; 0.745 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[5]           ; clk5       ; clk5     ; None                        ; None                      ; 0.704 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[3]           ; c24:inst10|count[5]           ; clk5       ; clk5     ; None                        ; None                      ; 0.695 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[0]           ; c24:inst10|count[2]~DUPLICATE ; clk5       ; clk5     ; None                        ; None                      ; 0.692 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[0]           ; c24:inst10|count[2]           ; clk5       ; clk5     ; None                        ; None                      ; 0.692 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[5]           ; c24:inst10|count[2]~DUPLICATE ; clk5       ; clk5     ; None                        ; None                      ; 0.678 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[5]           ; c24:inst10|count[2]           ; clk5       ; clk5     ; None                        ; None                      ; 0.678 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[2]~DUPLICATE ; c24:inst10|count[3]           ; clk5       ; clk5     ; None                        ; None                      ; 0.638 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[2]           ; c24:inst10|count[1]           ; clk5       ; clk5     ; None                        ; None                      ; 0.632 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[0]           ; c24:inst10|count[5]           ; clk5       ; clk5     ; None                        ; None                      ; 0.574 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[3]           ; c24:inst10|count[1]           ; clk5       ; clk5     ; None                        ; None                      ; 0.528 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[4]           ; c24:inst10|count[4]           ; clk5       ; clk5     ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[3]           ; c24:inst10|count[3]           ; clk5       ; clk5     ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[1]           ; clk5       ; clk5     ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[0]           ; c24:inst10|count[0]           ; clk5       ; clk5     ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[2]           ; clk5       ; clk5     ; None                        ; None                      ; 0.447 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[2]~DUPLICATE ; clk5       ; clk5     ; None                        ; None                      ; 0.446 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[4]           ; clk5       ; clk5     ; None                        ; None                      ; 0.439 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[1]           ; c24:inst10|count[3]           ; clk5       ; clk5     ; None                        ; None                      ; 0.437 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[5]           ; c24:inst10|count[5]           ; clk5       ; clk5     ; None                        ; None                      ; 0.396 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[2]~DUPLICATE ; c24:inst10|count[2]~DUPLICATE ; clk5       ; clk5     ; None                        ; None                      ; 0.396 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; c24:inst10|count[2]           ; c24:inst10|count[2]           ; clk5       ; clk5     ; None                        ; None                      ; 0.396 ns                ;
+-------+------------------------------------------------+-------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------+
; tco                                                                                   ;
+-------+--------------+------------+-------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                          ; To   ; From Clock ;
+-------+--------------+------------+-------------------------------+------+------------+
; N/A   ; None         ; 5.866 ns   ; c24:inst10|count[5]           ; pwm5 ; clk5       ;
; N/A   ; None         ; 5.835 ns   ; c24:inst10|count[2]~DUPLICATE ; pwm5 ; clk5       ;
; N/A   ; None         ; 5.823 ns   ; c24:inst|count[2]             ; pwm3 ; clk3       ;
; N/A   ; None         ; 5.798 ns   ; c24:inst9|count[4]            ; pwm4 ; clk4       ;
; N/A   ; None         ; 5.798 ns   ; c24:inst7|count[3]            ; pwm1 ; clk1       ;
; N/A   ; None         ; 5.795 ns   ; c24:inst|count[5]             ; pwm3 ; clk3       ;
; N/A   ; None         ; 5.782 ns   ; c24:inst8|count[3]            ; pwm2 ; clk2       ;
; N/A   ; None         ; 5.724 ns   ; c24:inst10|count[3]           ; pwm5 ; clk5       ;
; N/A   ; None         ; 5.702 ns   ; c24:inst10|count[4]           ; pwm5 ; clk5       ;
; N/A   ; None         ; 5.658 ns   ; c24:inst7|count[2]            ; pwm1 ; clk1       ;
; N/A   ; None         ; 5.625 ns   ; c24:inst|count[4]             ; pwm3 ; clk3       ;
; N/A   ; None         ; 5.608 ns   ; c24:inst8|count[5]            ; pwm2 ; clk2       ;
; N/A   ; None         ; 5.553 ns   ; c24:inst9|count[5]            ; pwm4 ; clk4       ;
; N/A   ; None         ; 5.548 ns   ; c24:inst|count[3]             ; pwm3 ; clk3       ;
; N/A   ; None         ; 5.507 ns   ; c24:inst7|count[5]            ; pwm1 ; clk1       ;
; N/A   ; None         ; 5.463 ns   ; c24:inst7|count[4]            ; pwm1 ; clk1       ;
; N/A   ; None         ; 5.390 ns   ; c24:inst8|count[4]            ; pwm2 ; clk2       ;
+-------+--------------+------------+-------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jul 29 12:37:50 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Block1 -c Block1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
    Info: Assuming node "clk2" is an undefined clock
    Info: Assuming node "clk3" is an undefined clock
    Info: Assuming node "clk4" is an undefined clock
    Info: Assuming node "clk5" is an undefined clock
Info: Clock "clk1" Internal fmax is restricted to 500.0 MHz between source register "c24:inst7|count[3]" and destination register "c24:inst7|count[2]~DUPLICATE"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.908 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y4_N15; Fanout = 7; REG Node = 'c24:inst7|count[3]'
            Info: 2: + IC(0.375 ns) + CELL(0.378 ns) = 0.753 ns; Loc. = LCCOMB_X39_Y4_N2; Fanout = 1; COMB Node = 'c24:inst7|count~271DUPLICATE'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.908 ns; Loc. = LCFF_X39_Y4_N3; Fanout = 4; REG Node = 'c24:inst7|count[2]~DUPLICATE'
            Info: Total cell delay = 0.533 ns ( 58.70 % )
            Info: Total interconnect delay = 0.375 ns ( 41.30 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 2.495 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk1~clkctrl'
                Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X39_Y4_N3; Fanout = 4; REG Node = 'c24:inst7|count[2]~DUPLICATE'
                Info: Total cell delay = 1.472 ns ( 59.00 % )
                Info: Total interconnect delay = 1.023 ns ( 41.00 % )
            Info: - Longest clock path from clock "clk1" to source register is 2.495 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 7; COMB Node = 'clk1~clkctrl'
                Info: 3: + IC(0.680 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X39_Y4_N15; Fanout = 7; REG Node = 'c24:inst7|count[3]'
                Info: Total cell delay = 1.472 ns ( 59.00 % )
                Info: Total interconnect delay = 1.023 ns ( 41.00 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk2" Internal fmax is restricted to 500.0 MHz between source register "c24:inst8|count[3]" and destination register "c24:inst8|count[5]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.398 ns