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📄 block1.map.rpt

📁 用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM
💻 RPT
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; Estimated ALUTs Unavailable                   ; 9                  ;
;                                               ;                    ;
; Total combinational functions                 ; 37                 ;
; Combinational ALUT usage by number of inputs  ;                    ;
;     -- 7 input functions                      ; 0                  ;
;     -- 6 input functions                      ; 9                  ;
;     -- 5 input functions                      ; 5                  ;
;     -- 4 input functions                      ; 15                 ;
;     -- <=3 input functions                    ; 8                  ;
;                                               ;                    ;
; Combinational ALUTs by mode                   ;                    ;
;     -- normal mode                            ; 37                 ;
;     -- extended LUT mode                      ; 0                  ;
;     -- arithmetic mode                        ; 0                  ;
;     -- shared arithmetic mode                 ; 0                  ;
;                                               ;                    ;
; Estimated ALUT/register pairs used            ; 46                 ;
;                                               ;                    ;
; Total registers                               ; 30                 ;
;     -- Dedicated logic registers              ; 30                 ;
;     -- I/O registers                          ; 0                  ;
;                                               ;                    ;
; Estimated ALMs:  partially or completely used ; 23                 ;
;                                               ;                    ;
; I/O pins                                      ; 10                 ;
; Maximum fan-out node                          ; c24:inst7|count[3] ;
; Maximum fan-out                               ; 6                  ;
; Total fan-out                                 ; 216                ;
; Average fan-out                               ; 2.81               ;
+-----------------------------------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |Block1                    ; 37 (0)            ; 30 (0)       ; 0                 ; 0            ; 0       ; 0         ; 0         ; 10   ; 0            ; |Block1             ; work         ;
;    |c24:inst10|            ; 6 (6)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|c24:inst10  ; work         ;
;    |c24:inst7|             ; 6 (6)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|c24:inst7   ; work         ;
;    |c24:inst8|             ; 8 (8)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|c24:inst8   ; work         ;
;    |c24:inst9|             ; 6 (6)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|c24:inst9   ; work         ;
;    |c24:inst|              ; 6 (6)             ; 6 (6)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|c24:inst    ; work         ;
;    |pwm2:inst3|            ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|pwm2:inst3  ; work         ;
;    |pwm3:inst4|            ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|pwm3:inst4  ; work         ;
;    |pwm4:inst5|            ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|pwm4:inst5  ; work         ;
;    |pwm5:inst6|            ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|pwm5:inst6  ; work         ;
;    |pwm:inst1|             ; 1 (1)             ; 0 (0)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |Block1|pwm:inst1   ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; c24:inst10|count[6..7]                 ; Stuck at GND due to stuck port data_in ;
; c24:inst9|count[6..7]                  ; Stuck at GND due to stuck port data_in ;
; c24:inst|count[6..7]                   ; Stuck at GND due to stuck port data_in ;
; c24:inst8|count[6..7]                  ; Stuck at GND due to stuck port data_in ;
; c24:inst7|count[6..7]                  ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 10 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 30    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 3:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |Block1|c24:inst7|count[3]  ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |Block1|c24:inst8|count[3]  ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |Block1|c24:inst|count[3]   ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |Block1|c24:inst9|count[3]  ;
; 3:1                ; 4 bits    ; 8 ALUTs       ; 8 ALUTs              ; 0 ALUTs                ; Yes        ; |Block1|c24:inst10|count[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jul 29 12:37:20 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Block1 -c Block1
Info: Found 2 design units, including 1 entities, in source file pwm2.vhd
    Info: Found design unit 1: pwm2-one
    Info: Found entity 1: pwm2
Info: Found 2 design units, including 1 entities, in source file pwm3.vhd
    Info: Found design unit 1: pwm3-one
    Info: Found entity 1: pwm3
Info: Found 2 design units, including 1 entities, in source file pwm4.vhd
    Info: Found design unit 1: pwm4-one
    Info: Found entity 1: pwm4
Info: Found 2 design units, including 1 entities, in source file pwm5.vhd
    Info: Found design unit 1: pwm5-one
    Info: Found entity 1: pwm5
Warning: Using design file Block1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Warning: Using design file pwm.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pwm-one
    Info: Found entity 1: pwm
Info: Elaborating entity "pwm" for hierarchy "pwm:inst1"
Warning: Using design file c24.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: c24-Behavioral
    Info: Found entity 1: c24
Info: Elaborating entity "c24" for hierarchy "c24:inst7"
Warning (10492): VHDL Process Statement warning at c24.vhd(24): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "pwm2" for hierarchy "pwm2:inst3"
Info: Elaborating entity "pwm3" for hierarchy "pwm3:inst4"
Info: Elaborating entity "pwm4" for hierarchy "pwm4:inst5"
Info: Elaborating entity "pwm5" for hierarchy "pwm5:inst6"
Warning (14130): Reduced register "c24:inst10|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst10|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst9|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst9|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst8|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst8|count[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst7|count[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "c24:inst7|count[7]" with stuck data_in port to stuck value GND
Info: Implemented 47 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 5 output pins
    Info: Implemented 37 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Tue Jul 29 12:37:24 2008
    Info: Elapsed time: 00:00:04


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