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<TD align=right>Overview | <A
href="http://www.opencores.org/projects/vga_lcd/Wishlist">Wishlist</A>
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<P><B><FONT color=#bf0000 size=+2>Project: VGA/LCD
Controller</FONT></B>
<P><B><FONT size=+1>Details</FONT></B>
<P>Category: <A
href="http://www.opencores.org/projects?category=video">Video
controller</A><BR>Last updated: 16/5/2003<BR>Created:
25/9/2001<BR>Wishbone compliant core: Yes<BR>Stage:
Production/Stable<BR>Mailing list: <A
href="http://www.opencores.org/forums/cores">Cores</A>
<P><B><FONT size=+1>Description</FONT></B>
<P>The OpenCores VGA/LCD Controller core is a WISHBONE revB.3
compliant embedded VGA core capable of driving CRT and LCD displays.
It supports user programmable resolutions and video timings, which
are limited only by the available WISHBONE bandwidth. Making it
compatible with almost all available LCD and CRT displays
<BR><BR>The core supports a number of color modes, including 32bpp,
24bpp, 16bpp, 8bpp gray-scale, and 8bpp-pseudo color. The video
memory is located outside the primary core, thus providing the most
flexible memory solution. It can be located on-chip or off-chip,
shared with the system抯 main memory (VGA on demand) or be dedicated
to the VGA system. The color lookup table is, as of core version
2.0, incorporated into the color-processor block. <BR><BR>Pixel data
is fetched automatically via the Wishbone revB.3 Master interface,
making this an ideal 損rogram-and-forget?video solution. More
demanding video applications like streaming video or video games can
benefit from the video-bank-switching function, which reduces
flicker and cluttered images by automatically switching between
video-memory pages and/or color lookup tables on each vertical
retrace. <BR>The core can interrupt the host on each horizontal
and/or vertical synchronization pulse. The horizontal, vertical and
composite synchronization polarization levels, as well as the
blanking polarization level are user programmable. <BR><BR>
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<P><B><FONT size=+1>Features</FONT></B>
<P>
<UL type=disc>
<LI>CRT and LCD display support
<LI>24bit Standard VGA interface<O:P></O:P></SPAN>
<UL type=circle>
<LI>Separate VSYNC/HSYNC and combined CSYNC synchronization
signals
<LI>Composite BLANK signal<O:P></O:P></SPAN>
<LI>TripleDisplay support</LI></UL>
<LI>12bit Interface
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<LI>Compatible with DVI transmitters and 12bit VGA ADCs
<LI>4 different output modes
<LI>Can be used simultaneous with the 24bit interface</LI></UL>
<LI>User programmable video resolutions <O:P></O:P></SPAN>
<LI>User programmable video timing
<LI>User programmable video control signals polarization levels
<LI>32bpp, 24bpp and 16bpp color modes
<LI>8bit gray-scale and 8bit pseudo-color modes
<LI>Supports video- and/or color-lookup-table bankswitching during
vertical retrace
<LI>32bit WISHBONE revB.3 compliant slave and master interfaces
<LI>Operates from a wide range of input clock frequencies
<LI>Static synchronous design
<LI>Fully synthesizeable </LI></UL>See the on-line documentation
(current revision 1.2) for more information.<BR>
<P><B><FONT size=+1>Status</FONT></B>
<P>
<UL>
<LI>VGA/LCD core v2.0 is ready and available in verilog from
OpenCores CVS via cvsweb or via cvsget.
<LI>Low level abstraction layer available in C from CVS.
<LI>Character simulation software is currently under development.
</LI></UL>
<P><B><FONT size=+1>Project news</FONT></B>
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<TD vAlign=top><B>Date</B></TD>
<TD vAlign=top><B>News</B></TD></TR>
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<TD vAlign=top>16/5/2003</TD>
<TD vAlign=top>12bit (DVI) interface added.<BR></TD></TR>
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<TD vAlign=top>20/3/2003</TD>
<TD vAlign=top>Added support for WISHBONE revB.3
Registered Feedback Cycles <BR>Changed VGA Timing
generator; made is smaller (less gates) and more
intuitive.<BR></TD></TR>
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<TD vAlign=top>20/4/2002</TD>
<TD vAlign=top>VGA Timing generator changes, vertical
timing changed. <BR>Read new documentation for
changes.<BR></TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
<P><B><FONT size=+1>Synthesis results</FONT></B>
<P>LeonardoSpectrum synthesis results for Altera devices. Aimed at
100MHz clock operation (wishbone clock & pixel clock), area
optimezed. <BR><BR>
<UL>
<LI>FLEX: EPF10K50E-1: 1112lcells, 16080mem_bits@82MHz wishbone,
100MHz pixel clock
<LI>ACEX: EPF1K50-1: 1113lcells, 16080mem_bits@85MHz wishbone,
107MHz pixel clock
<LI>APEX: EPF20K60E-1: 1142lcells, 16080mem_bits@47MHz wishbone,
119MHz pixel clock</LI></UL>
<P><B><FONT size=+1>Downloads</FONT></B>
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<TD vAlign=top><B>Date</B></TD>
<TD vAlign=top><B>Description</B></TD>
<TD vAlign=top><B>Link</B></TD></TR>
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<TD vAlign=top>23/9/2003</TD>
<TD vAlign=top>Documentation<BR></TD>
<TD vAlign=top><A
href="http://www.opencores.org/cgi-bin/cvsget.cgi/vga_lcd/doc/vga_core.pdf">vga_core.pdf</A></TD></TR>
<TR bgColor=#f0f0f0>
<TD vAlign=top>20/10/2003</TD>
<TD vAlign=top>VGA/LCD Core in verilog<BR></TD>
<TD vAlign=top><A
href="http://www.opencores.org/cgi-bin/cvsget.cgi/vga_lcd">vga_lcd</A></TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
<P><B><FONT size=+1>Maintainers</FONT></B>
<P>
<UL>
<LI><A href="http://www.opencores.org/people/rherveille">Richard
Herveille</A></LI></UL>
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