mdioif_uartout_bp.v

UART接口的VERILOG代码

//+FHDR---------------------------------------------------------------
//Copyright(c) 2008 NEUSOFT , Inc.All rights reserved
//NEUSOFT Confidential Proprietary
//--------------------------------------------------------------------
//FILE NAME : 
//DEPARTMENT 
//AUTHOR :Siping Liu
//--------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPITION
//1.0 2008--4.22
//--------------------------------------------------------------------
//KEYWORDS 
//--------------------------------------------------------------------
//PURPOSE : generate 
//--------------------------------------------------------------------
//PARAMETERS 
//PARRAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//--------------------------------------------------------------------
//REUSE ISSUES 
//Reset Strategy
//Clock Domains:50MHz
//Critical Timing
//Test Features
//Asynchronous
//Synthesizable
//Other
//-HDR----------------------------------------------------------------

module mdioif_uartout_bp (
	clk,
	reset,
	
	mdioif_uartout_shiften,
	mdioif_uartout_updata,
	mdioif_uartout_crcen,
	mdioif_uartout_dselect,
	mdioif_uartout_doen,
	mdioif_mdiocon_dinreg,
	
	mdioif_uart_tx
	);

input	clk;
input	reset;

input	mdioif_uartout_shiften;
input	mdioif_uartout_updata;
input mdioif_uartout_crcen;
input	mdioif_uartout_dselect;
input[1:0]	mdioif_uartout_doen;
input[15:0]	mdioif_mdiocon_dinreg;

output	mdioif_uart_tx;

reg	mdioif_uart_tx;

////////////////////////
//error or data select
reg[23:0]	mdioif_uartout_derror;
reg[7:0]	mdioif_uartout_crc;
reg[23:0]	mdioif_uartout_shiftreg;

//crc process
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_crc <= 8'd0;
	else
	begin
		if(mdioif_uartout_crcen)
			mdioif_uartout_crc <= mdioif_mdiocon_dinreg[15:8] ^ mdioif_mdiocon_dinreg[7:0];
		else
			mdioif_uartout_crc <= 8'd0;
	end
end

////select
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_derror <= 24'd0;
	else
	begin
		if(mdioif_uartout_dselect)
			mdioif_uartout_derror <= {mdioif_uartout_crc,mdioif_mdiocon_dinreg[7:0],mdioif_mdiocon_dinreg[15:8]};
		else
			mdioif_uartout_derror <= {8'h5a,8'h5a,8'h5a};
	end
end

//shift register process
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_shiftreg <= 24'd0;
	else
	begin
		if(mdioif_uartout_updata)
			mdioif_uartout_shiftreg <= mdioif_uartout_derror;
		else
		begin
			if(mdioif_uartout_shiften)
				mdioif_uartout_shiftreg <= {mdioif_uartout_shiftreg[23],mdioif_uartout_shiftreg[23:1]};
			else
				mdioif_uartout_shiftreg <= mdioif_uartout_shiftreg;
		end
	end
end

//data out put process
always@(posedge clk)
begin
	if(!reset)
		mdioif_uart_tx <= 1'b1;
	else
	begin
		if(mdioif_uartout_doen == 2'b01)
			mdioif_uart_tx <= 1'b0;
		else
		begin
			if(mdioif_uartout_doen == 2'b10)
				mdioif_uart_tx <= 1'b1;
			else
			begin
				if(mdioif_uartout_doen == 2'b11)
					mdioif_uart_tx <= mdioif_uartout_shiftreg[0];
				else
					mdioif_uart_tx <= mdioif_uart_tx;
			end
		end	
	end
end

endmodule