mdioif_uartout_cp.v

UART接口的VERILOG代码

//+FHDR---------------------------------------------------------------
//Copyright(c) 2008 NEUSOFT , Inc.All rights reserved
//NEUSOFT Confidential Proprietary
//--------------------------------------------------------------------
//FILE NAME : 
//DEPARTMENT 
//AUTHOR :Siping Liu
//--------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPITION
//1.0 2008--
//--------------------------------------------------------------------
//KEYWORDS 
//--------------------------------------------------------------------
//PURPOSE : generate 
//--------------------------------------------------------------------
//PARAMETERS 
//PARRAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//--------------------------------------------------------------------
//REUSE ISSUES 
//Reset Strategy
//Clock Domains:50MHz
//Critical Timing
//Test Features
//Asynchronous
//Synthesizable
//Other
//-HDR----------------------------------------------------------------

`include	"mdioif_macro.v"

module mdioif_uartout_cp(
	clk,
	reset,
	
	mdioif_uartout_crcen,
	mdioif_uartin_error,
	
	mdioif_uartout_dselect,
	mdioif_uartout_updata,
	mdioif_uartout_doen,
	
	mdioif_uartout_shiften
	);
input	clk;
input reset;

input	mdioif_uartout_crcen;
input	mdioif_uartin_error;

output	mdioif_uartout_dselect;
output	mdioif_uartout_updata;
output[1:0]	mdioif_uartout_doen;
output	mdioif_uartout_shiften;      

reg	mdioif_uartout_dselect;
reg	mdioif_uartout_updata;
reg	mdioif_uartout_shiften;	
reg[1:0]	mdioif_uartout_doen;

//reg	mdioif_uartout_pcrcen;
reg[4:0]	mdioif_uartout_doct;
reg[`UART_DWITH-1:0]	mdioif_uartout_bpsct;

////1
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_dselect <= 1'b0;
	else
		mdioif_uartout_dselect <= mdioif_uartout_crcen;
end

////2
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_updata <= 1'b0;
	else
	begin
		if(mdioif_uartout_doct == 5'd0)
		begin
			if(mdioif_uartin_error | mdioif_uartout_dselect)
				mdioif_uartout_updata <= 1'b1;
			else
				mdioif_uartout_updata <= 1'b0;
		end
		else
			mdioif_uartout_updata <= 1'b0;
	end
end

////3
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_doct <= 5'd0;
	else
	begin
		if(mdioif_uartout_doct == 5'd0)
		begin
			if(mdioif_uartout_updata)
				mdioif_uartout_doct <= 5'd30;
			else
				mdioif_uartout_doct <= 5'd0;
		end
		else
		begin
			if(mdioif_uartout_bpsct == (`UART_IBPS + 2))
				mdioif_uartout_doct <= mdioif_uartout_doct - 1'b1;
			else
				mdioif_uartout_doct <= mdioif_uartout_doct;
		end
	end
end

////4
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_bpsct <= `UART_IBPS;
	else
	begin
		if(mdioif_uartout_doct != 5'd0)
		begin
			if(mdioif_uartout_bpsct == `UART_BPS)
				mdioif_uartout_bpsct <= 5'd0;
			else
				mdioif_uartout_bpsct <= mdioif_uartout_bpsct + 1'b1;
		end
		else
			mdioif_uartout_bpsct <= 5'd0;
	end
end

/////5
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_doen <= 2'b00;
	else
	begin
		if(mdioif_uartout_bpsct == (`UART_IBPS + 1))
		begin
			if((mdioif_uartout_doct == 5'd10)|(mdioif_uartout_doct == 5'd20)|(mdioif_uartout_doct == 5'd30))
				mdioif_uartout_doen <= 2'b01;
			else
			begin
				if((mdioif_uartout_doct == 5'd1) | (mdioif_uartout_doct == 5'd11) | (mdioif_uartout_doct == 5'd21))
					mdioif_uartout_doen <= 2'b10;
				else
					mdioif_uartout_doen <= 2'b11;
			end
		end  
		else
			mdioif_uartout_doen <= 2'b00;
	end
end

////6
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartout_shiften <= 1'b0;
	else
	begin
		if(mdioif_uartout_doen == 2'b11)
			mdioif_uartout_shiften <= 1'b1;
		else
			mdioif_uartout_shiften <= 1'b0;
	end
end
endmodule