mdioif_uartin_cp.v

UART接口的VERILOG代码

//+FHDR---------------------------------------------------------------
//Copyright(c) 2008 NEUSOFT , Inc.All rights reserved
//NEUSOFT Confidential Proprietary
//--------------------------------------------------------------------
//FILE NAME : 
//DEPARTMENT 
//AUTHOR :Siping Liu
//--------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPITION
//1.0 2008--
//--------------------------------------------------------------------
//KEYWORDS 
//--------------------------------------------------------------------
//PURPOSE : generate 
//--------------------------------------------------------------------
//PARAMETERS 
//PARRAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//--------------------------------------------------------------------
//REUSE ISSUES 
//Reset Strategy
//Clock Domains:50MHz
//Critical Timing
//Test Features
//Asynchronous
//Synthesizable
//Other
//-HDR----------------------------------------------------------------

`include	"mdioif_macro.v"
module	mdioif_uartin_cp(
	clk,
	reset,
	
	mdioif_uart_rx,
	mdioif_uartin_data,
	mdioif_uartin_dav_8,
	mdioif_uartin_doen,
	mdioif_uartin_shiftreg,
	
	mdioif_uartin_cten,
	mdioif_uartin_dselect,
	mdioif_uartin_daven,
	mdioif_uartin_shiften,
	mdioif_uartin_crcen,
	mdioif_uartin_compen,
	mdioif_uartin_error
	);
input	clk;
input	reset;

input	mdioif_uart_rx;

input	mdioif_uartin_data;
input	mdioif_uartin_doen;
input	mdioif_uartin_dav_8;
input[63:0]	mdioif_uartin_shiftreg;

output	mdioif_uartin_cten;
output	mdioif_uartin_dselect;
output	mdioif_uartin_daven;
output	mdioif_uartin_shiften;
output	mdioif_uartin_crcen;
output	mdioif_uartin_compen;
output	mdioif_uartin_error;


reg	mdioif_uartin_cten;
reg	mdioif_uartin_dselect;
reg	mdioif_uartin_daven;
reg	mdioif_uartin_shiften;
reg	mdioif_uartin_crcen;
reg	mdioif_uartin_compen;
reg	mdioif_uartin_error;
///////////////////////
reg	mdioif_uartin_bpscten;
reg	mdioif_uartin_cerror;
reg[2:0]	mdioif_uartin_sampct;  //sample counter
reg[5:0]	mdioif_uartin_bct;     //register of the receved bits counter
reg[5:0]	mdioif_uartin_adge;    
reg[`UART_DFWITH-1:0]	mdioif_uartin_bpsct;

/////detect the negedge of the data in;
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_adge <= 6'b111111;
	else
		mdioif_uartin_adge <= {mdioif_uartin_adge[4:0],mdioif_uart_rx};
end

///////1
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_bpscten <= 1'b0;
	else
	begin
		if(mdioif_uartin_bpscten == 1'b0)
		begin
			if(mdioif_uartin_adge == 6'b111000)
				mdioif_uartin_bpscten <= 1'b1;
			else
				mdioif_uartin_bpscten <= mdioif_uartin_bpscten;
		end
		else
		begin
			if(mdioif_uartin_bct == 6'd50 & (mdioif_uartin_bpsct == (`UART_DTBPS + 5)))
				mdioif_uartin_bpscten <= 1'b0;
			else
				mdioif_uartin_bpscten <= mdioif_uartin_bpscten;
		end
	end
end

/////////2
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_bpsct <= `UART_IDFBPS;
	else
	begin
		if(mdioif_uartin_bpscten)
		begin
			if(mdioif_uartin_bpsct == `UART_DFBPS)
				mdioif_uartin_bpsct <= `UART_IDFBPS;
			else
				mdioif_uartin_bpsct <= mdioif_uartin_bpsct + 1'b1;
		end
		else
			mdioif_uartin_bpsct <= `UART_IDFBPS;
	end
end

//////////3
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_bct <= 6'd0;
	else
	begin
		if(mdioif_uartin_bpsct == `UART_DTBPS)
	//	begin
	//		if(mdioif_uartin_bct == 6'd50)
	//			mdioif_uartin_bct <= 6'd0;
	//		else
				mdioif_uartin_bct <= mdioif_uartin_bct + 1'b1;
	//	end
		else
		begin
			if(!mdioif_uartin_bpscten)
				mdioif_uartin_bct <= 6'd0;
			else
			mdioif_uartin_bct <= mdioif_uartin_bct;			
		end
	end
end

//////4
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_cten <= 1'b0;
	else
	begin
		if(mdioif_uartin_bpsct == `UART_DTBPS)
			mdioif_uartin_cten <= 1'b1;
		else
			mdioif_uartin_cten <= 1'b0;
	end
end

////5
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_sampct <= 3'd4;
	else
	begin
		if(mdioif_uartin_cten)
		begin
			if(mdioif_uartin_sampct == 3'd4)
				mdioif_uartin_sampct <= 3'd0;
			else
				mdioif_uartin_sampct <= mdioif_uartin_sampct +1'b1;
		end
		else
			mdioif_uartin_sampct <= mdioif_uartin_sampct;
	end
end

////6
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_dselect <= 1'b0;
	else
	begin
		if(mdioif_uartin_bpsct == (`UART_DTBPS + 2))
		begin
			if(mdioif_uartin_sampct == 3'd4)
				mdioif_uartin_dselect <= 1'b1;
			else
				mdioif_uartin_dselect <= 1'b0;
		end			
		else
			mdioif_uartin_dselect <= 1'b0;
	end
end

//////7
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_daven <= 1'b0;
	else
		mdioif_uartin_daven <= mdioif_uartin_dselect;
end

////8
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_shiften <= 1'b0;
	else
	begin
		if(mdioif_uartin_bct == 6'd50 & (mdioif_uartin_bpsct == (`UART_DTBPS + 4)))
		begin
			if(mdioif_uartin_data & (!mdioif_uartin_dav_8))
				mdioif_uartin_shiften <=1'b1;
			else
				mdioif_uartin_shiften <= 1'b0;
		end
		else
			mdioif_uartin_shiften <= 1'b0;
	end
end

////9
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_crcen <= 1'b0;
	else
	begin
		if(mdioif_uartin_shiften)
		begin
			if(mdioif_uartin_shiftreg[63:32] == 32'hffffffff)
				mdioif_uartin_crcen <= 1'b1;
			else
				mdioif_uartin_crcen <= 1'b0;
		end
		else
			mdioif_uartin_crcen <= 1'b0;
	end
end

////10
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_compen <= 1'b0;
	else
		mdioif_uartin_compen <= mdioif_uartin_crcen;
end

///11
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_cerror <= 1'b0;
	else
		mdioif_uartin_cerror <= mdioif_uartin_compen;
end

////12
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_error <= 1'b0;
	else
	begin
		if(mdioif_uartin_cerror)
		begin
			if(!mdioif_uartin_doen)
				mdioif_uartin_error <= 1'b1;
			else
				mdioif_uartin_error <= 1'b0;
		end
		else
			mdioif_uartin_error<= 1'b0;
	end
end

endmodule