mdioif_uartin_bp.v

UART接口的VERILOG代码

//+FHDR---------------------------------------------------------------
//Copyright(c) 2008 NEUSOFT , Inc.All rights reserved
//NEUSOFT Confidential Proprietary
//--------------------------------------------------------------------
//FILE NAME : 
//DEPARTMENT 
//AUTHOR :Siping Liu 
//--------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPITION
//1.0 2008--
//--------------------------------------------------------------------
//KEYWORDS 
//--------------------------------------------------------------------
//PURPOSE : generate 
//--------------------------------------------------------------------
//PARAMETERS 
//PARRAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//--------------------------------------------------------------------
//REUSE ISSUES 
//Reset Strategy
//Clock Domains:50MHz
//Critical Timing
//Test Features
//Asynchronous
//Synthesizable
//Other
//-HDR----------------------------------------------------------------
module mdioif_uartin_bp(
	clk,
	reset,
	
	mdioif_uart_rx,
	mdioif_uartin_cten,
	mdioif_uartin_dselect,
	mdioif_uartin_daven,
	mdioif_uartin_shiften,
	mdioif_uartin_crcen,
	mdioif_uartin_compen,
	
	mdioif_uartin_doen,
	mdioif_uartin_data,
	mdioif_uartin_dav_8,
	mdioif_uartin_shiftreg
	);
	
input	clk;
input	reset;

input	mdioif_uart_rx;

input	mdioif_uartin_cten;
input	mdioif_uartin_dselect;
input	mdioif_uartin_daven;
input	mdioif_uartin_shiften;
input	mdioif_uartin_crcen;
input	mdioif_uartin_compen;

output	mdioif_uartin_doen;
output	mdioif_uartin_data;
output	mdioif_uartin_dav_8;
output[63:0]	mdioif_uartin_shiftreg;

reg	mdioif_uartin_doen;
reg	mdioif_uartin_data;
reg[63:0]	mdioif_uartin_shiftreg;
///////////////////////////////////////////////////
reg[2:0]	mdioif_uartin_coun;
reg[7:0]	mdioif_uartin_crc;
reg[8:0]	mdioif_uartin_dav;


assign	mdioif_uartin_dav_8 = mdioif_uartin_dav[0];
/////the connter of data in 
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_coun <= 3'd0;
	else
	begin
		if(mdioif_uartin_dselect)
			mdioif_uartin_coun <= 3'd0;
		else
		begin
			if(mdioif_uartin_cten)
			begin
				if(mdioif_uart_rx)
					mdioif_uartin_coun <= mdioif_uartin_coun + 1'b1;
				else
				  mdioif_uartin_coun <= mdioif_uartin_coun;
			end
			else
				mdioif_uartin_coun <= mdioif_uartin_coun;
		end
	end
end

////compare to catch a available bit data
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_data <= 1'b0;
	else
	begin
		if(!mdioif_uartin_dselect)
			mdioif_uartin_data <= mdioif_uartin_data;
		else
		begin
			if(mdioif_uartin_coun >3'd2)
				mdioif_uartin_data <= 1'b1;
			else
				mdioif_uartin_data <= 1'b0;
		end
	end
end

////the 8 bits available data shift register 

always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_dav <= 9'b111111111;
	else
	begin
		if(mdioif_uartin_daven)
			mdioif_uartin_dav <= {mdioif_uartin_data,mdioif_uartin_dav[8:1]};
		else
			mdioif_uartin_dav <= mdioif_uartin_dav;
	end
end


////the 72 bits shift register
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_shiftreg <= 64'd0;
	else
	begin
		if(mdioif_uartin_shiften)
			mdioif_uartin_shiftreg <= {mdioif_uartin_shiftreg[63:0],mdioif_uartin_dav[7:0]};
		else
			mdioif_uartin_shiftreg <= mdioif_uartin_shiftreg;
	end
end

////crc operate
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_crc <= 8'd0;
	else
	begin
		if(!mdioif_uartin_crcen)
			mdioif_uartin_crc <= mdioif_uartin_crc;
		else
				mdioif_uartin_crc <= (((mdioif_uartin_shiftreg[39:32] ^ mdioif_uartin_shiftreg[31:24]) 
														^ mdioif_uartin_shiftreg[23:16]) ^ mdioif_uartin_shiftreg[15:8]);
	end
end

////after crc to compare
always@(posedge clk)
begin
	if(!reset)
		mdioif_uartin_doen <= 1'b0;
	else
	begin
		if(!mdioif_uartin_compen)
			mdioif_uartin_doen <=1'b0;
		else
		begin
			if(mdioif_uartin_shiftreg[7:0] == mdioif_uartin_crc)
				mdioif_uartin_doen <=1'b1;
			else
					mdioif_uartin_doen <=1'b0;
		end
		
	end
end

endmodule