pcilynx.h

IEE1394 火线接口驱动 for linux

#define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
#define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
#define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
#define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
#define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
#define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
#define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)

#define LINK_ID                           0xf00
#define LINK_ID_BUS(id)                   (id<<22)
#define LINK_ID_NODE(id)                  (id<<16)

#define LINK_CONTROL                      0xf04
#define LINK_CONTROL_BUSY                 (1<<29)
#define LINK_CONTROL_TX_ISO_EN            (1<<26)
#define LINK_CONTROL_RX_ISO_EN            (1<<25)
#define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
#define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
#define LINK_CONTROL_RESET_TX             (1<<21)
#define LINK_CONTROL_RESET_RX             (1<<20)
#define LINK_CONTROL_CYCMASTER            (1<<11)
#define LINK_CONTROL_CYCSOURCE            (1<<10)
#define LINK_CONTROL_CYCTIMEREN           (1<<9)
#define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
#define LINK_CONTROL_SNOOP_ENABLE         (1<<6)

#define CYCLE_TIMER                       0xf08

#define LINK_PHY                          0xf0c
#define LINK_PHY_READ                     (1<<31)
#define LINK_PHY_WRITE                    (1<<30)
#define LINK_PHY_ADDR(addr)               (addr<<24)
#define LINK_PHY_WDATA(data)              (data<<16)
#define LINK_PHY_RADDR(addr)              (addr<<8)


#define LINK_INT_STATUS                   0xf14
#define LINK_INT_ENABLE                   0xf18
/* status and enable have identical bit numbers */
#define LINK_INT_LINK_INT                 (1<<31)
#define LINK_INT_PHY_TIMEOUT              (1<<30)
#define LINK_INT_PHY_REG_RCVD             (1<<29)
#define LINK_INT_PHY_BUSRESET             (1<<28)
#define LINK_INT_TX_RDY                   (1<<26)
#define LINK_INT_RX_DATA_RDY              (1<<25)
#define LINK_INT_ISO_STUCK                (1<<20)
#define LINK_INT_ASYNC_STUCK              (1<<19)
#define LINK_INT_SENT_REJECT              (1<<17)
#define LINK_INT_HDR_ERR                  (1<<16)
#define LINK_INT_TX_INVALID_TC            (1<<15)
#define LINK_INT_CYC_SECOND               (1<<11)
#define LINK_INT_CYC_START                (1<<10)
#define LINK_INT_CYC_DONE                 (1<<9)
#define LINK_INT_CYC_PENDING              (1<<8)
#define LINK_INT_CYC_LOST                 (1<<7)
#define LINK_INT_CYC_ARB_FAILED           (1<<6)
#define LINK_INT_GRF_OVERFLOW             (1<<5)
#define LINK_INT_ITF_UNDERFLOW            (1<<4)
#define LINK_INT_ATF_UNDERFLOW            (1<<3)
#define LINK_INT_ISOARB_FAILED            (1<<0) 

/* PHY specifics */
#define PHY_VENDORID_TI                 0x800028
#define PHY_PRODUCTID_TSB41LV03         0x000000


/* this is the physical layout of a PCL, its size is 128 bytes */
struct ti_pcl {
        u32 next;
        u32 async_error_next;
        u32 user_data;
        u32 pcl_status;
        u32 remaining_transfer_count;
        u32 next_data_buffer;
        struct {
                u32 control;
                u32 pointer;
        } buffer[13] __attribute__ ((packed));
} __attribute__ ((packed));

#include <linux/stddef.h>
#define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))


#ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM

static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           const struct ti_pcl *pcl)
{
        int i;
        u32 *in = (u32 *)pcl;
        u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));

        for (i = 0; i < 32; i++, out++, in++) {
                writel(*in, out);
        }
}

static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           struct ti_pcl *pcl)
{
        int i;
        u32 *out = (u32 *)pcl;
        u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));

        for (i = 0; i < 32; i++, out++, in++) {
                *out = readl(in);
        }
}

static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
{
        return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
}

#else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */

static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           const struct ti_pcl *pcl)
{
        memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
                    (u32 *)pcl, sizeof(struct ti_pcl));
}

static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                           struct ti_pcl *pcl)
{
        memcpy_le32((u32 *)pcl,
                    (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
                    sizeof(struct ti_pcl));
}

static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
{
        return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
}

#endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */


#if defined (CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined (__BIG_ENDIAN)
typedef struct ti_pcl pcltmp_t;

static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                                      pcltmp_t *tmp)
{
        get_pcl(lynx, pclid, tmp);
        return tmp;
}

static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                              pcltmp_t *tmp)
{
        put_pcl(lynx, pclid, tmp);
}

#else
typedef int pcltmp_t; /* just a dummy */

static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                                      pcltmp_t *tmp)
{
        return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
}

static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
                              pcltmp_t *tmp)
{
}
#endif


static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
                               int dmachan)
{
        reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
                  pcl_bus(lynx, pclid) + idx * 4);
        reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
                  DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
}

static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
{
        run_sub_pcl(lynx, pclid, 0, dmachan);
}

#define PCL_NEXT_INVALID (1<<0)

/* transfer commands */
#define PCL_CMD_RCV            (0x1<<24)
#define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
#define PCL_CMD_XMT            (0x2<<24)
#define PCL_CMD_UNFXMT         (0xc<<24)
#define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
#define PCL_CMD_LBUS_TO_PCI    (0x9<<24)

/* aux commands */
#define PCL_CMD_NOP            (0x0<<24)
#define PCL_CMD_LOAD           (0x3<<24)
#define PCL_CMD_STOREQ         (0x4<<24)
#define PCL_CMD_STORED         (0xb<<24)
#define PCL_CMD_STORE0         (0x5<<24)
#define PCL_CMD_STORE1         (0x6<<24)
#define PCL_CMD_COMPARE        (0xe<<24)
#define PCL_CMD_SWAP_COMPARE   (0xf<<24)
#define PCL_CMD_ADD            (0xd<<24)
#define PCL_CMD_BRANCH         (0x7<<24)

/* BRANCH condition codes */
#define PCL_COND_DMARDY_SET    (0x1<<20)
#define PCL_COND_DMARDY_CLEAR  (0x2<<20)

#define PCL_GEN_INTR           (1<<19)
#define PCL_LAST_BUFF          (1<<18)
#define PCL_LAST_CMD           (PCL_LAST_BUFF)
#define PCL_WAITSTAT           (1<<17)
#define PCL_BIGENDIAN          (1<<16)
#define PCL_ISOMODE            (1<<12)


#define _(x) (__constant_cpu_to_be32(x))

static quadlet_t lynx_csr_rom[] = {
/* bus info block     offset (hex) */
        _(0x04046aaf), /* info/CRC length, CRC              400  */
        _(0x31333934), /* 1394 magic number                 404  */
        _(0xf064a000), /* misc. settings                    408  */
        _(0x08002850), /* vendor ID, chip ID high           40c  */
        _(0x0000ffff), /* chip ID low                       410  */
/* root directory */
        _(0x00095778), /* directory length, CRC             414  */
        _(0x03080028), /* vendor ID (Texas Instr.)          418  */
        _(0x81000008), /* offset to textual ID              41c  */
        _(0x0c000200), /* node capabilities                 420  */
        _(0x8d00000e), /* offset to unique ID               424  */
        _(0xc7000010), /* offset to module independent info 428  */
        _(0x04000000), /* module hardware version           42c  */
        _(0x81000014), /* offset to textual ID              430  */
        _(0x09000000), /* node hardware version             434  */
        _(0x81000018), /* offset to textual ID              438  */
/* module vendor ID textual */
        _(0x00070812), /* CRC length, CRC                   43c  */
        _(0x00000000), /*                                   440  */
        _(0x00000000), /*                                   444  */
        _(0x54455841), /* "Texas Instruments"               448  */
        _(0x5320494e), /*                                   44c  */
        _(0x53545255), /*                                   450  */
        _(0x4d454e54), /*                                   454  */
        _(0x53000000), /*                                   458  */
/* node unique ID leaf */
        _(0x00022ead), /* CRC length, CRC                   45c  */
        _(0x08002850), /* vendor ID, chip ID high           460  */
        _(0x0000ffff), /* chip ID low                       464  */
/* module dependent info */
        _(0x0005d837), /* CRC length, CRC                   468  */
        _(0x81000012), /* offset to module textual ID       46c  */
        _(0x81000017), /* textual descriptor                470  */
        _(0x39010000), /* SRAM size                         474  */
        _(0x3a010000), /* AUXRAM size                       478  */
        _(0x3b000000), /* AUX device                        47c  */
/* module textual ID */
        _(0x000594df), /* CRC length, CRC                   480  */
        _(0x00000000), /*                                   484  */
        _(0x00000000), /*                                   488  */
        _(0x54534231), /* "TSB12LV21"                       48c  */
        _(0x324c5632), /*                                   490  */
        _(0x31000000), /*                                   494  */
/* part number */
        _(0x00068405), /* CRC length, CRC                   498  */
        _(0x00000000), /*                                   49c  */
        _(0x00000000), /*                                   4a0  */
        _(0x39383036), /* "9806000-0001"                    4a4  */
        _(0x3030302d), /*                                   4a8  */
        _(0x30303031), /*                                   4ac  */
        _(0x20000001), /*                                   4b0  */
/* module hardware version textual */
        _(0x00056501), /* CRC length, CRC                   4b4  */
        _(0x00000000), /*                                   4b8  */
        _(0x00000000), /*                                   4bc  */
        _(0x5453424b), /* "TSBKPCITST"                      4c0  */
        _(0x50434954), /*                                   4c4  */
        _(0x53540000), /*                                   4c8  */
/* node hardware version textual */
        _(0x0005d805), /* CRC length, CRC                   4d0  */
        _(0x00000000), /*                                   4d4  */
        _(0x00000000), /*                                   4d8  */
        _(0x54534232), /* "TSB21LV03"                       4dc  */
        _(0x314c5630), /*                                   4e0  */
        _(0x33000000)  /*                                   4e4  */
};

#undef _