hwconf.c

美国Diamond公司开发的串口通信模块Vxworks6.6 BSP

    /* non vxbPciAutoConfig() values */
    { "pciConfigMechanism",HCF_RES_INT, { (void *)(1)}},
    { "maxBusSet", HCF_RES_INT, { (void *)PCI_MAX_BUS } },
    { "autoConfig",HCF_RES_INT, { (void *)(FALSE)}},

#ifdef	DRV_INTCTLR_IOAPIC
    { "funcPirqEnable", HCF_RES_ADDR, { (void *)sysPciPirqEnable}},
#endif	/* DRV_INTCTLR_IOAPIC */

#ifdef INCLUDE_USB
    { "cpuToBus", HCF_RES_ADDR, { (void *) usbMemToPci}},
    { "busToCpu", HCF_RES_ADDR, { (void *) usbPciToMem}},
#endif

    { "vmStateMaskForAll",HCF_RES_INT, { (void *)(VM_STATE_MASK_FOR_ALL)}},
    { "vmStateForPci",HCF_RES_INT, { (void *)(VM_STATE_FOR_PCI)}}

    };
#define pentiumPci0Num NELEMENTS(pentiumPci0Resources)

#if defined (DRV_TIMER_I8253)
struct hcfResource i8253DevResources[] = {
    { "regBase", HCF_RES_INT, {(void *)PIT_BASE_ADR} },
    { "clkFreq", HCF_RES_INT, {(void *)PIT_CLOCK} },
#ifdef SYMMETRIC_IO_MODE
    { "intr0", HCF_RES_INT, {(void *)INUM_TO_IVEC (INT_NUM_IOAPIC_IRQ2)}},
#else
    { "intr0", HCF_RES_INT, {(void *)INUM_TO_IVEC (INT_NUM_IRQ0)}},
#endif
    { "intr0Level", HCF_RES_INT, {(void *)PIT0_INT_LVL}},
    { "clkRateMin", HCF_RES_INT, {(void *)SYS_CLK_RATE_MIN} },
    { "clkRateMax", HCF_RES_INT, {(void *)SYS_CLK_RATE_MAX} },
    { "regInterval",HCF_RES_INT, {(void *)PIT_REG_ADDR_INTERVAL} }
};

#define i8253DevNum NELEMENTS(i8253DevResources)
#endif /* DRV_TIMER_I8253 */

#if defined (DRV_TIMER_LOAPIC)
struct hcfResource loApicTimerResources[] = {
    { "regBase",   HCF_RES_INT, {(void *)(LOAPIC_BASE)} },
    { "intr",      HCF_RES_INT, {(void *)INUM_TO_IVEC (INT_NUM_LOAPIC_TIMER)}},
    { "intrLevel", HCF_RES_INT, {(void *)INT_NUM_LOAPIC_TIMER}},
    { "clkFreq",   HCF_RES_INT, {(void *)APIC_TIMER_CLOCK_HZ} },
    { "clkRateMin",HCF_RES_INT, {(void *)SYS_CLK_RATE_MIN} },
    { "clkRateMax",HCF_RES_INT, {(void *)SYS_CLK_RATE_MAX} },
};

#define loApicTimerDevNum NELEMENTS(loApicTimerResources)
#endif /* DRV_TIMER_LOAPIC */

#if defined (DRV_TIMER_IA_TIMESTAMP)
struct hcfResource iaTimestampResources[] = {
    { "regBase",   HCF_RES_INT, {(void *)0} },
    { "clkFreq",   HCF_RES_INT, {(void *)IA_TIMESTAMP_CLK_FREQ} },
#ifdef _WRS_VX_SMP
    { "clkRateMin", HCF_RES_INT, {(void *)IA_TIMESTAMP_CLK_FREQ} },
    { "clkRateMax", HCF_RES_INT, {(void *)IA_TIMESTAMP_CLK_FREQ} }
#else
    { "clkRateMin", HCF_RES_INT, {(void *)1000} },
    { "clkRateMax", HCF_RES_INT, {(void *)IA_TIMESTAMP_CLK_FREQ} }
#endif
};

#define iaTimestampNum NELEMENTS(iaTimestampResources)
#endif /* DRV_TIMER_IA_TIMESTAMP */

#if defined (DRV_TIMER_MC146818)
struct hcfResource mc146818DevResources[] = {
    { "regBase", HCF_RES_INT, {(void *)RTC_INDEX} },
    { "irq", HCF_RES_INT, {(void *)INUM_TO_IVEC(INT_NUM_RTC)}},
    { "irqLevel", HCF_RES_INT, {(void *)RTC_INT_LVL}},
    { "clkFreq", HCF_RES_INT, {(void *)MC146818_CLK_FREQ} },
    { "clkRateMin", HCF_RES_INT, {(void *)2} },
    { "clkRateMax", HCF_RES_INT, {(void *)8192} },
};

#define mc146818DevNum NELEMENTS(mc146818DevResources)
#endif /* DRV_TIMER_MC146818 */

#if defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE) 
struct hcfResource mpApicResources[] = {
    { "regBase",   HCF_RES_INT, {(void *)ERROR} },
#ifdef	SYMMETRIC_IO_MODE
    { "symmetricIoMode",   HCF_RES_INT, {(void *)TRUE} },
#endif	/* SYMMETRIC_IO_MODE */
};
#define mpApicNum NELEMENTS(mpApicResources)

LOCAL const struct intrCtlrInputs loApicInputs[] = {
    { VXB_INTR_DYNAMIC, "yn", 0, 0 },
};

LOCAL const struct intrCtlrCpu loApicCpu[] = {
    { COM2_INT_LVL, 1 },
};

LOCAL struct hcfResource loApicIntrResources[] = {
    { "regBase",           HCF_RES_INT,  {(void *)LOAPIC_BASE} },
    { "input",	           HCF_RES_ADDR, {(void *)&loApicInputs[0] } },
    { "inputTableSize",    HCF_RES_INT,  {(void *)NELEMENTS(loApicInputs) } },
    { "cpuRoute",          HCF_RES_ADDR, {(void *)&loApicCpu[0] } },
    { "cpuRouteTableSize", HCF_RES_INT,  {(void *)NELEMENTS(loApicCpu) } },
#ifdef  SYMMETRIC_IO_MODE
    { "symmetricIoMode",   HCF_RES_INT, {(void *)TRUE} },
#endif  /* SYMMETRIC_IO_MODE */
#ifdef  VIRTUAL_WIRE_MODE
    { "virtualWireMode",   HCF_RES_INT, {(void *)TRUE} },
#endif  /* VIRTUAL_WIRE_MODE */
}; 
#define loApicIntrNum NELEMENTS(loApicIntrResources)
#endif /* VIRTUAL_WIRE_MODE || SYMMETRIC_IO_MODE */

#if defined (SYMMETRIC_IO_MODE) 
struct hcfResource ioApicIntr0Resources[] = {
    { "regBase", HCF_RES_INT, {(void *)IOAPIC_BASE0} },
};

#define ioApicIntr0Num NELEMENTS(ioApicIntr0Resources)

struct hcfResource ioApicIntr1Resources[] = {
    { "regBase", HCF_RES_INT, {(void *)(IOAPIC_BASE1)} },
};

#define ioApicIntr1Num NELEMENTS(ioApicIntr1Resources)
#endif /* SYMMETRIC_IO_MODE */

NVRAM_SEGMENT flNvRam0Segments[] = {
    { "bootline", 0, NV_BOOT_OFFSET, BOOT_LINE_SIZE },
};

const struct hcfResource flNvRam0Resources[] = {
    { "regBase",        HCF_RES_INT, { (void *)-1 } },
    { "segments",       HCF_RES_ADDR, { (void *)&flNvRam0Segments[0] } },
    { "numSegments",	HCF_RES_INT, { (void *)NELEMENTS(flNvRam0Segments) } },
    { "size",           HCF_RES_INT, { (void *)NV_RAM_SIZE } },
    { "fileName",       HCF_RES_STRING, { (void *)"/ata1a/nvram.txt" } },
};
#define flNvRam0Num NELEMENTS(flNvRam0Resources)

#ifdef INCLUDE_DRV_STORAGE_INTEL_ICH
IMPORT ATA_RESOURCE ataResources[];
IMPORT ATA_TYPE ataTypes[][];
IMPORT void sysIchAtaInit (ATA_CTRL *);

const struct hcfResource ata0Resources[] = {
    { "ataResources",   HCF_RES_ADDR, { (void *)&ataResources[0] } },
    { "ataTypes",       HCF_RES_ADDR, { (void *)&ataTypes[0][0] } },
    { "dev00",          HCF_RES_STRING, { (void *)"/ata0a" } },
    { "sysAtaInit",     HCF_RES_ADDR, { (void *)sysIchAtaInit } },
};
#define ata0Num NELEMENTS(ata0Resources)
#endif /* INCLUDE_DRV_STORAGE_INTEL_ICH */

const struct hcfDevice hcfDeviceList[] = {
#if defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE) 
    { "mpApic", 0, VXB_BUSID_PLB, 0, mpApicNum, mpApicResources },
    { "loApicIntr", 0, VXB_BUSID_PLB, 0, loApicIntrNum, loApicIntrResources },
#if defined (SYMMETRIC_IO_MODE) 
    { "ioApicIntr", 0, VXB_BUSID_PLB, 0, ioApicIntr0Num, ioApicIntr0Resources },
    { "ioApicIntr", 1, VXB_BUSID_PLB, 0, ioApicIntr1Num, ioApicIntr1Resources },
#endif /* SYMMETRIC_IO_MODE */
#endif /* VIRTUAL_WIRE_MODE || SYMMETRIC_IO_MODE */
#ifdef INCLUDE_NE2000_VXB_END
    { "ene", 0, VXB_BUSID_PLB, 0, ne2000Num, ne2000Resources },
#endif
    { "ns16550", 0, VXB_BUSID_PLB, 0, pentiumi82501Num, pentiumi82501Resources },
    { "ns16550", 1, VXB_BUSID_PLB, 0, pentiumi82502Num, pentiumi82502Resources },
    { "pentiumPci", 0, VXB_BUSID_NEXUS, 0, pentiumPci0Num, pentiumPci0Resources },
#if defined (INCLUDE_PC_CONSOLE) || defined (INCLUDE_WINDML)
    { "i8042Kbd", 0, VXB_BUSID_PLB, 0, pentiumi8042KbdNum, pentiumi8042KbdResources },
    { "i8042Mse", 0, VXB_BUSID_PLB, 0, pentiumi8042MseNum, pentiumi8042MseResources },
    { "m6845Vga", 0, VXB_BUSID_PLB, 0, pentiumM6845VgaNum, pentiumM6845VgaResources },
#endif /* INCLUDE_PC_CONSOLE || INCLUDE_WINDML */
#if defined (DRV_TIMER_I8253)
    { "i8253TimerDev", 0, VXB_BUSID_PLB, 0, i8253DevNum, i8253DevResources },
#endif /* DRV_TIMER_I8253 */
#if defined (DRV_TIMER_LOAPIC)
    { "loApicTimer", 0, VXB_BUSID_PLB, 0, loApicTimerDevNum, loApicTimerResources },
#endif /* DRV_TIMER_LOAPIC */
#if defined (DRV_TIMER_IA_TIMESTAMP)
    { "iaTimestamp", 0, VXB_BUSID_PLB, 0, iaTimestampNum, iaTimestampResources },
#endif /* DRV_TIMER_IA_TIMESTAMP */
#if defined (DRV_TIMER_MC146818)
    { "mc146818Rtc", 0, VXB_BUSID_PLB, 0, mc146818DevNum, mc146818DevResources },
#endif /* DRV_TIMER_MC146818 */
    { "fileNvRam", 0, VXB_BUSID_PLB, 0, flNvRam0Num, flNvRam0Resources },
#ifdef INCLUDE_DRV_STORAGE_INTEL_ICH
    { "intelIchAta", 0, VXB_BUSID_PCI, 0, ata0Num, ata0Resources },
#endif /* INCLUDE_DRV_STORAGE_INTEL_ICH */
};
const int hcfDeviceNum = NELEMENTS(hcfDeviceList);

VXB_INST_PARAM_OVERRIDE sysInstParamTable[] =
    {
    { NULL, 0, NULL, VXB_PARAM_END_OF_LIST, {(void *)0} }
    };