hwconf.c

美国Diamond公司开发的串口通信模块Vxworks6.6 BSP

/* hwconf.c - Hardware configuration support module */

/*
 * Copyright (c) 2005-2007 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01x,12oct07,h_k  changed maxBusSet number to PCI_MAX_BUS from 0.
01w,28sep07,scm  WIND00105939.
01v,12sep07,pmr  include keyboard, mouse, and video resources for WindML.
01u,07sep07,ami  entries added for USB Support
01t,23aug07,pmr  DMA init for Intel ICH Storage
01s,22aug07,pmr  VxBus ATA
01r,30jul07,scm  SMP TIMESTAMP work...
01q,18jul07,tor  VxBus NvRam support
01p,15jul07,tor  dynamic intr support
01o,21jun07,tor  prelim integrate intCtlr with VxBus interrupt routing
01n,19jun07,h_k  added symmetricIoMode and virtualWireMode.
01m,14jun07,dtr  Import sysPciPirqEnable function.
01l,25may07,h_k  added parameters for PCI.
01k,23may07,dlk  Use INT_NUM_IOAPIC_IRQ2 rather than INT_NUM_IRQ0
                 for i8253 timer 0 in SYMMETRIC_IO_MODE.
01j,23mar07,scm  create hcfResource array for local and io Apics...
01i,05mar07,dtr  Do not auto config PCI by default.
01h,05mar07,pdg  added timer support
01g,02mar07,pmr  Add VxBus PC Console
01g,28feb07,dtr  Support latest vxBus PCI Autoconfog.
01f,17jan07,wap  Add NE2000 VxBus END driver
01e,24Oct06,tor  added kbd & mouse support for WindML
01d,14dec05,pdg  added "clkFreq" resource to uart devices
01c,09nov05,mdo  Add parameter system table
01b,26oct05,mdo  Add bspSerialClkFrequencyGet needed for the uart on the PLB
01a,29sep05,mdo  Fix gnu warnings
*/


/* includes */

#include <vxWorks.h>

#include <vxBusLib.h>
#include <hwif/vxbus/vxBus.h>
#include <hwif/vxbus/vxbPlbLib.h>
#include <hwif/vxbus/vxbPciLib.h>
#include <hwif/vxbus/vxbIntrCtlr.h>
#include <hwif/util/vxbParamSys.h>
#include <hwif/vxbus/hwConf.h>
#include <hwif/util/vxbNonVol.h>

#ifdef INCLUDE_USB
extern UINT32 usbMemToPci (void * pAddr);
extern void * usbPciToMem (UINT32 addr);
#endif

#include "config.h"

#include "../src/hwif/h/console/pcConsole.h"

#if defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE)
#include <hwif/intCtlr/vxbMpApic.h>
#endif /* VIRTUAL_WIRE_MODE || SYMMETRIC_IO_MODE */

IMPORT VOID sysPciPirqEnable (BOOL);

#define PCI_CLK_FREQ 1843200
#ifndef PCI_MEM_ADRS
    #define PCI_MEM_ADRS    0x20000000
    #define PCI_MEM_SIZE    0x00010000
#endif /* PCI_MEM_ADRS */

#ifndef PCI_MEMIO_ADRS
    #define PCI_MEMIO_ADRS  0x20010000
    #define PCI_MEMIO_SIZE  0x1fff0000
#endif /* PCI_MEMIO_ADRS */

#ifndef PCI_ISA_IO_ADRS
    #define PCI_ISA_IO_ADRS 0x40000000
    #define PCI_ISA_IO_SIZE 0x60000000
#endif /* PCI_ISA_IO_ADRS */

#ifndef PCI_IO_ADRS
    #define PCI_IO_ADRS 0xa0000000
    #define PCI_IO_SIZE 0x5ff80000
#endif /* PCI_IO_ADRS */

#if defined (DRV_TIMER_MC146818)
#define MC146818_CLK_FREQ	4194304	
#endif /* DRV_TIMER_MC146818 */

#if defined (DRV_TIMER_IA_TIMESTAMP)

/* NOTE: Can only set timestamp frequency for UP images using
 * the TSC, SMP images use HPET...
 * 
 * Values greater than 130000000, and TSC frequency calculation 
 * begin to drift far from requested frequency.
 */

#ifndef _WRS_VX_SMP
#define IA_TIMESTAMP_CLK_FREQ	124974000 
#else
/* NOTE: With HPET the counter clock period is a fixed constsant held in the
 * HPET's General Capabilities and ID Register. The frequency is calculated
 * f = 1/T, so f = 1/(COUNTER_CLK_PERIOD * 10^-15), must convert
 * femptoseconds to seconds...
 */

#define IA_TIMESTAMP_CLK_FREQ	14242000  
#endif
#endif

#ifdef INCLUDE_NE2000_VXB_END
const struct hcfResource ne2000Resources[] =
    {
        { "regBase", HCF_RES_INT, {(void *)IO_ADRS_ENE} },
        { "intr", HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_ENE))} },
        { "intrLevel", HCF_RES_INT, {(void *)INT_LVL_ENE} },
    };
#define ne2000Num NELEMENTS(ne2000Resources)
#endif

/* vxBus resource files for onboard UARTS */

const struct hcfResource pentiumi82501Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM1_BASE_ADR} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_COM1))} },
        { "regInterval", HCF_RES_INT, {(void *)UART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)COM1_INT_LVL} },
        { "clkFreq",	 HCF_RES_INT, {(void *)PCI_CLK_FREQ} }
    };
#define pentiumi82501Num NELEMENTS(pentiumi82501Resources)

const struct hcfResource pentiumi82502Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM2_BASE_ADR} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_COM2))} },
        { "regInterval", HCF_RES_INT, {(void *)UART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)COM2_INT_LVL} },
        { "clkFreq",	 HCF_RES_INT, {(void *)PCI_CLK_FREQ} }
    };
#define pentiumi82502Num NELEMENTS(pentiumi82502Resources)

#if defined (INCLUDE_PC_CONSOLE) || defined (INCLUDE_WINDML)
/* keyboard Controller 8042 */

const struct hcfResource pentiumi8042KbdResources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)DATA_8042} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_KBD))} },
        { "regInterval", HCF_RES_INT, {(void *)4} }, 
        { "irqLevel",    HCF_RES_INT, {(void *)KBD_INT_LVL} },
	{ "mode",	 HCF_RES_INT, {(void *)KEYBRD_MODE} }
    };
#define pentiumi8042KbdNum NELEMENTS(pentiumi8042KbdResources)

const struct hcfResource pentiumi8042MseResources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)DATA_8042} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_MSE))} },
        { "regInterval", HCF_RES_INT, {(void *)4} },
        { "irqLevel",    HCF_RES_INT, {(void *)MSE_INT_LVL} }
    };
#define pentiumi8042MseNum NELEMENTS(pentiumi8042MseResources)

/* VGA card */

const struct hcfResource pentiumM6845VgaResources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *) CTRL_SEL_REG} },
        { "memBase",     HCF_RES_INT, {(void *) CTRL_MEM_BASE} },
        { "colorMode",   HCF_RES_INT, {(void *) COLOR_MODE} },
        { "colorSetting",HCF_RES_INT, {(void *) DEFAULT_ATR} },
    };
#define pentiumM6845VgaNum NELEMENTS(pentiumM6845VgaResources)
#endif  /* INCLUDE_PC_CONSOLE || INCLUDE_WINDML */

const struct hcfResource pentiumPci0Resources[] = 
    {

    { "regBase", HCF_RES_INT, {(void *)0x00} },
    { "mem32Addr", HCF_RES_ADDR, { (void *)PCI_MEM_ADRS } },
    { "mem32Size", HCF_RES_INT, { (void *)PCI_MEM_SIZE } },
    { "memIo32Addr", HCF_RES_ADDR, { (void *)PCI_MEMIO_ADRS } },
    { "memIo32Size", HCF_RES_INT, { (void *)PCI_MEMIO_SIZE } },
    { "io32Addr", HCF_RES_ADDR, { (void *)PCI_IO_ADRS } },
    { "io32Size", HCF_RES_INT, { (void *)PCI_IO_SIZE } }, 
    { "io16Addr", HCF_RES_ADDR, { (void *)PCI_ISA_IO_ADRS } },
    { "io16Size", HCF_RES_INT, { (void *)PCI_ISA_IO_SIZE } }, 
    { "fbbEnable", HCF_RES_INT, { (void *)TRUE } },
    { "cacheSize", HCF_RES_INT, { (void *)(_CACHE_ALIGN_SIZE / 4) } }, 
    { "autoIntRouteSet", HCF_RES_INT, { (void *)TRUE } },