stm32f4xx_flash.c
来自「STM3240G-Eval_uCOS-III」· C语言 代码 · 共 137 行
C
137 行
/**
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* - FLASH Interface configuration
* - FLASH Memory Programming
* - Option Bytes Programming
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
*
* This driver provides functions to configure and program the FLASH
* memory of all STM32F4xx devices.
* These functions are split in 4 groups:
*
* 1. FLASH Interface configuration functions: this group includes the
* management of the following features:
* - Set the latency
* - Enable/Disable the prefetch buffer
* - Enable/Disable the Instruction cache and the Data cache
* - Reset the Instruction cache and the Data cache
*
* 2. FLASH Memory Programming functions: this group includes all needed
* functions to erase and program the main memory:
* - Lock and Unlock the FLASH interface
* - Erase function: Erase sector, erase all sectors
* - Program functions: byte, half word, word and double word
*
* 3. Option Bytes Programming functions: this group includes all needed
* functions to manage the Option Bytes:
* - Set/Reset the write protection
* - Set the Read protection Level
* - Set the BOR level
* - Program the user Option Bytes
* - Launch the Option Bytes loader
*
* 4. Interrupts and flags management functions: this group
* includes all needed functions to:
* - Enable/Disable the FLASH interrupt sources
* - Get flags status
* - Clear flags
* - Get FLASH operation status
* - Wait for last FLASH operation
*
* @endverbatim
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_flash.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup FLASH
* @brief FLASH driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Functions
* @{
*/
/** @defgroup FLASH_Group1 FLASH Interface configuration functions
* @brief FLASH Interface configuration functions
*
@verbatim
===============================================================================
FLASH Interface configuration functions
===============================================================================
This group includes the following functions:
- void FLASH_SetLatency(uint32_t FLASH_Latency)
To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device.
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
|***************|****************|****************|*****************|*****************|*****************************+
| | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|Max Parallelism| x32 | x16 | x8 | x64 |
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|PSIZE[1:0] | 10 | 01 | 00 | 11 |
+-------------------------------------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0
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