hwctxt.cpp

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

            // Turn off the codec and amps
            BSPAudioStopCodecInput(bus, path);

            // Stop SSI transmit
            BSPAudioStopSsiInput(VOICE_CODEC_SSI);

            break;
    }

    return rc;
}

#endif // #ifdef AUDIO_RECORDING_ENABLED


//-----------------------------------------------------------------------------
//
//  Function: BSPAudioSetOutputGain
//
//
//  Parameters:
//      bus	- Audio bus to be used for output SSI1 / SSI2
//	  path      - Audio out path selection
//  Returns:
//      TRUE or FALSE
//
//-----------------------------------------------------------------------------
BOOL HardwareContext::BSPAudioSetOutputGain(AUDIO_BUS bus, const DWORD dwGain)
{
    UNREFERENCED_PARAMETER(dwGain);
    UNREFERENCED_PARAMETER(bus);

    DEBUGMSG(ZONE_FUNCTION, (_T("+HardwareContext::BSPAudioSetOutputGain\n")));

    DEBUGMSG(ZONE_FUNCTION, (_T("-HardwareContext::BSPAudioSetOutputGain\n")));

    return TRUE;
}


#ifdef AUDIO_RECORDING_ENABLED

//-----------------------------------------------------------------------------
//
//  Function: BSPAudioSetInputGain
//
//
//  Parameters:
//      bus	- Audio bus to be used for output SSI1 / SSI2
//	  dwGain  - Audio Input gain selection
//  Returns:
//      TRUE or FALSE
//
//-----------------------------------------------------------------------------
BOOL HardwareContext::BSPAudioSetInputGain(AUDIO_BUS bus, const DWORD dwGain)
{
    UNREFERENCED_PARAMETER(dwGain);
    UNREFERENCED_PARAMETER(bus);

    DEBUGMSG(ZONE_FUNCTION, (_T("+HardwareContext::BSPAudioSetInputGain\n")));

    DEBUGMSG(ZONE_FUNCTION, (_T("-HardwareContext::BSPAudioSetInputGain\n")));

    return TRUE;
}

#endif // #ifdef AUDIO_RECORDING_ENABLED

//------------------------------------------------------------------------------
//
//  FUNCTION:       SetPortConfig
//
//  DESCRIPTION:    This function is used to set the cofiguration of
//                  a desired AUDMUX port.
//
//  PARAMETERS:
//                  port - AUDMUX port ID
//                  config - pointer to AUDMUX port configuration
//
//  RETURNS:        None
//
//------------------------------------------------------------------------------
void HardwareContext::SetPortConfig(AUDMUX_PORT_ID port, AUDMUX_PORT_CONFIG *config)
{
    UINT32 				reg;

    DEBUGMSG(1, (TEXT("AudmuxClass::SetPortConfig+\r\n")));

    reg = 0;
    if(config->txFsInput == TRUE)
    {
        // Set TFSDIR to input
        reg = CSP_BITFVAL(AUDMUX_HPCR_TFSDIR, AUDMUX_HPCR_TFSDIR_INPUT);
    }
    else
    {
        // Set TFSDIR to output
        reg = (UINT32)CSP_BITFVAL(AUDMUX_HPCR_TFSDIR, AUDMUX_HPCR_TFSDIR_OUTPUT);
    }
    if(config->txClkInput == TRUE)
    {
        // Set TCLKDIR to input
        CSP_BITFINS(reg, AUDMUX_HPCR_TCLKDIR, AUDMUX_HPCR_TCLKDIR_INPUT);
    }
    else
    {
        // Set TCLKDIR to 1 output
        CSP_BITFINS(reg, AUDMUX_HPCR_TCLKDIR, AUDMUX_HPCR_TCLKDIR_OUTPUT);
    }
    // If fs and clk source is from rx of port,
    if(config->txFsClkFromRx == TRUE)
    {
        CSP_BITFINS(reg, AUDMUX_HPCR_TFCSEL, (AUDMUX_HPCR_TFCSEL_FROM_RX | config->txFsClkSrcPort));
    }
    else
    {
        CSP_BITFINS(reg, AUDMUX_HPCR_TFCSEL, (AUDMUX_HPCR_TFCSEL_FROM_TX | config->txFsClkSrcPort));
    }

    if (config->rxFsInput == TRUE)
    {
        // Set RFSDIR as input
        // When set as input, the RFCSEL settings are ignored.
        CSP_BITFINS(reg, AUDMUX_HPCR_RFSDIR, AUDMUX_HPCR_RFSDIR_INPUT);
    }
    else
    {
        // Set RFSDIR as output
        DEBUGMSG(1, (TEXT("2. reg=0x%x\r\n"), reg));
    }
    // If fs and clk source is from rx of port,
    if (config->rxClkInput == TRUE)
    {
        // Set RCLKDIR to input
        // When set as input, the RFCSEL settings are ignored.
        CSP_BITFINS(reg, AUDMUX_HPCR_RCLKDIR, AUDMUX_HPCR_RCLKDIR_INPUT);
    }
    else
    {
        // Set RCLKDIR to output
        CSP_BITFINS(reg, AUDMUX_HPCR_RCLKDIR, AUDMUX_HPCR_RCLKDIR_OUTPUT);
    }
    if(config->rxFsClkFromRx == TRUE)
    {
        CSP_BITFINS(reg, AUDMUX_HPCR_RFCSEL, AUDMUX_HPCR_RFCSEL_FROM_RX | config->rxFsClkSrcPort);
    }
    else
    {
        CSP_BITFINS(reg, AUDMUX_HPCR_RFCSEL, AUDMUX_HPCR_RFCSEL_FROM_TX | config->rxFsClkSrcPort);
    }

    // Select port source for receiving data from
    CSP_BITFINS(reg, AUDMUX_HPCR_RXDSEL, config->rxDataSrcPort);

    if (config->syncModeEn == TRUE)
    {
        // Default configuration to synchronous mode
        CSP_BITFINS(reg, AUDMUX_HPCR_SYN, AUDMUX_HPCR_SYN_SYNC);
    }
    else
        CSP_BITFINS(reg, AUDMUX_HPCR_SYN, AUDMUX_HPCR_SYN_ASYNC);

    // Only Ports 3,4,5,6 are capable of Tx/Rx switch
    if((config->txRxSwitchEn == TRUE) && (port >= AUDMUX_PORT_ID_HOST3))
    {

        	CSP_BITFINS(reg, AUDMUX_HPCR_TXRXEN, AUDMUX_HPCR_TXRXEN_SWITCH);
    }
    else
    {
        CSP_BITFINS(reg, AUDMUX_HPCR_TXRXEN, AUDMUX_HPCR_TXRXEN_NO_SWITCH);
    }

    DEBUGMSG(1, (TEXT("reg=0x%x\r\n"), reg));
    switch(port)
    {
        case AUDMUX_PORT_ID_HOST1:
            //m_pAUDMUX->HPCR1 = reg;
            OUTREG32(&m_pAUDMUX->HPCR1, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->HPCR1));
            break;
        case AUDMUX_PORT_ID_HOST2:
            //m_pAUDMUX->HPCR2 = reg;
            OUTREG32(&m_pAUDMUX->HPCR2, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->HPCR2));
            break;
        case AUDMUX_PORT_ID_HOST3:
            //m_pAUDMUX->HPCR3 = reg;
            OUTREG32(&m_pAUDMUX->HPCR3, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->HPCR3));
            break;
        case AUDMUX_PORT_ID_PERI1:
            //m_pAUDMUX->PPCR1 = reg;
            OUTREG32(&m_pAUDMUX->PPCR1, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->PPCR1));
            break;
        case AUDMUX_PORT_ID_PERI2:
            //m_pAUDMUX->PPCR2 = reg;
            OUTREG32(&m_pAUDMUX->PPCR2, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->PPCR2));
            break;
        case AUDMUX_PORT_ID_PERI3:
            //m_pAUDMUX->PPCR3 = reg;
            OUTREG32(&m_pAUDMUX->PPCR3, reg);
            DEBUGMSG(1, (TEXT("AUDMUX port[%d]=0x%08x\r\n"), port, m_pAUDMUX->PPCR3));
            break;
        default:
            ERRORMSG(1, (TEXT("Invalid audmux port selected!\r\n"), port));
            break;
    }

}

//-----------------------------------------------------------------------------
//
//  Function: BSPAudioRoute
//
//  This function configures the Audio MUX to connect/disconnect the SSI
//  to the external power management IC.
//
//  Parameters:
//
//
//  Returns:
//      None.
//
//-----------------------------------------------------------------------------
void HardwareContext::BSPAudioRoute(void)
{
    AUDMUX_PORT_CONFIG  audmuxConfig;

   // Configure Host port 2 for:
    // 1. TX data sink from Peripheral port 5,
    // 2. TX FS/CLK from peripheral port5
    // 3. Synchronous mode enabled
    audmuxConfig.txFsInput = FALSE;      // Codec is FS/CLK master
    audmuxConfig.txClkInput = FALSE;     // Codec is FS/CLK master
    audmuxConfig.txFsClkSrcPort = AUDMUX_PORT_ID_PERI2;
    audmuxConfig.txFsClkFromRx = FALSE;
    audmuxConfig.rxFsInput = FALSE;     // Not used. Set as input
    audmuxConfig.rxClkInput = FALSE;    // Not used. Set as input
    audmuxConfig.rxFsClkSrcPort = AUDMUX_PORT_ID_PERI2; // Ignored
    audmuxConfig.rxFsClkFromRx = FALSE;
    audmuxConfig.rxDataSrcPort = AUDMUX_PORT_ID_PERI2;
    audmuxConfig.syncModeEn = TRUE;
    audmuxConfig.txRxSwitchEn = FALSE;
    audmuxConfig.intNetworkEn = FALSE;

    SetPortConfig(AUDMUX_PORT_ID_HOST2, &audmuxConfig);


     // Configure peripheral port5:
    // 1. Rx data source to host port 2
    // 2. Rx CLK & FS master
    audmuxConfig.txFsInput = TRUE;      // Not used. Set as input
    audmuxConfig.txClkInput = TRUE;     // Not used. Set as input
    audmuxConfig.txFsClkSrcPort = AUDMUX_PORT_ID_PERI2; // Ignored
    audmuxConfig.txFsClkFromRx = FALSE;
    audmuxConfig.rxFsInput = TRUE;      // Codec is FS/CLK master
    audmuxConfig.rxClkInput = TRUE;     // Codec is FS/CLK master
    audmuxConfig.rxFsClkSrcPort = AUDMUX_PORT_ID_PERI2; // Ignored
    audmuxConfig.rxFsClkFromRx = FALSE;
    audmuxConfig.rxDataSrcPort = AUDMUX_PORT_ID_HOST2;
    audmuxConfig.syncModeEn = TRUE;
    audmuxConfig.txRxSwitchEn = FALSE;
    audmuxConfig.intNetworkEn = FALSE;

    SetPortConfig(AUDMUX_PORT_ID_PERI2, &audmuxConfig);

#if defined(AUDIO_RECORDING_ENABLED)

          ////////////////////////////////////
    //  AUDMUX SETTING
    ///////////////////////////////////
    // Configure AUDMUX host port1:
    // 1. TxFS and TxCLK is output selected from Port 4
    // 2. RxFS and RxCLK is output
    // 3. Synchronous mode enabled

    audmuxConfig.txFsInput = FALSE;
    audmuxConfig.txClkInput = FALSE;
    audmuxConfig.txFsClkSrcPort = AUDMUX_PORT_ID_PERI1;
    audmuxConfig.txFsClkFromRx = FALSE;
    audmuxConfig.rxFsInput = FALSE;
    audmuxConfig.rxClkInput = FALSE;
    audmuxConfig.rxFsClkSrcPort = AUDMUX_PORT_ID_PERI1;
    audmuxConfig.rxFsClkFromRx = FALSE;
    audmuxConfig.rxDataSrcPort = AUDMUX_PORT_ID_PERI1;
    audmuxConfig.syncModeEn = TRUE;
    audmuxConfig.txRxSwitchEn = FALSE;
    audmuxConfig.intNetworkEn = FALSE;

    SetPortConfig(AUDMUX_PORT_ID_HOST1, &audmuxConfig);


    // Configure peripheral port4:
    // 1. Rx data source to host port 1
    // 2. Rx CLK & FS master
    audmuxConfig.txFsInput = TRUE;      // Not used. Set as input
    audmuxConfig.txClkInput = TRUE;     // Not used. Set as input
    audmuxConfig.txFsClkSrcPort = AUDMUX_PORT_ID_PERI1; // Ignored
    audmuxConfig.txFsClkFromRx = FALSE;
    audmuxConfig.rxFsInput = TRUE;      // Codec is FS/CLK master
    audmuxConfig.rxClkInput = TRUE;     // Codec is FS/CLK master
    audmuxConfig.rxFsClkSrcPort = AUDMUX_PORT_ID_PERI1; // Ignored
    audmuxConfig.rxFsClkFromRx = FALSE;
    audmuxConfig.rxDataSrcPort = AUDMUX_PORT_ID_HOST1;
    audmuxConfig.syncModeEn = TRUE;
    audmuxConfig.txRxSwitchEn = FALSE;
    audmuxConfig.intNetworkEn = FALSE;

    SetPortConfig(AUDMUX_PORT_ID_PERI1, &audmuxConfig);

#endif

    DEBUGMSG(1, (TEXT("AUDMUX configured!\r\n")));


}

//-----------------------------------------------------------------------------
//
// Function: BSPSSIConfigGPIO
//
// This function is to configures SSI GPIO pins.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bIR
//          [in] TRUE if SIR. FALSE if not SIR.
//      bEnable
//          [in] TRUE if enable Uart GPIO pins. FALSE if disable Uart
//                GPIO pins.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPSSIConfigGPIO(ULONG HWAddr, BOOL bEnable)
{
    BOOL result = FALSE;
    DDK_GPIO_CFG  cfg;

   switch (HWAddr) {
            case CSP_BASE_REG_PA_SSI1:
                DDK_GPIO_SET_CONFIG(cfg, SSI1);
                break;
            case CSP_BASE_REG_PA_SSI2:
                DDK_GPIO_SET_CONFIG(cfg, SSI2);
                break;
            default:
                return result;
    }

    if (bEnable)
    {
        if(DDKGpioEnable(&cfg) == FALSE) {
            ERRORMSG(1, (TEXT("Cannot enable SSI gpio!\r\n")));
            goto CleanUp;
        }
    }
    else {
        if(DDKGpioDisable(&cfg) == FALSE) {
            ERRORMSG (1, (TEXT("Cannot Disable SSI gpio!\r\n")));
            goto CleanUp;
        }
    }

    result = TRUE;

CleanUp:
    return result;
}