📄 ddk_clk.c
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//
// Copyright (C) 2006-2007, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: ddk_clk.c
//
// This file contains the PLLCRC DDK interface that is used by applications and
// other drivers to access the capabilities of the PLLCRC driver.
//
//-----------------------------------------------------------------------------
#include <windows.h>
#include <ceddk.h>
#include "bsp.h"
//-----------------------------------------------------------------------------
// External Functions
//-----------------------------------------------------------------------------
// External Variables
//-----------------------------------------------------------------------------
// Defines
//-----------------------------------------------------------------------------
// Types
//-----------------------------------------------------------------------------
// Global Variables
//-----------------------------------------------------------------------------
// Local Variables
static BSP_ARGS *g_pBspArgs = NULL;
//-----------------------------------------------------------------------------
// Local Functions
//-----------------------------------------------------------------------------
//
// Function: BSPClockDealloc
//
// This function deallocates the data structures required for interaction
// with the clock configuration hardware.
//
// Parameters:
// None.
//
// Returns:
// Returns TRUE.
//
//-----------------------------------------------------------------------------
BOOL BSPClockDealloc(void)
{
// Unmap peripheral address space
if (g_pBspArgs == NULL) {
MmUnmapIoSpace(g_pBspArgs, sizeof(BSP_ARGS));
g_pBspArgs = NULL;
}
return TRUE;
}
//-----------------------------------------------------------------------------
//
// Function: BSPClockAlloc
//
// This function allocates the data structures required for interaction
// with the clock configuration hardware.
//
// Parameters:
// None.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL BSPClockAlloc(void)
{
BOOL rc = FALSE;
PHYSICAL_ADDRESS phyAddr;
if (g_pBspArgs == NULL) {
phyAddr.QuadPart = IMAGE_BOOT_RAM_PA_START;
// Map peripheral physical address to virtual address
g_pBspArgs = (BSP_ARGS *) MmMapIoSpace(phyAddr,
sizeof(BSP_ARGS), FALSE);
// Check if virtual mapping failed
if (g_pBspArgs == NULL) {
DBGCHK((_T("CSPDDK")), FALSE);
ERRORMSG(1, (_T("BSPClockAlloc: MmMapIoSpace failed!\r\n")));
goto cleanUp;
}
}
rc = TRUE;
cleanUp:
if (!rc) BSPClockDealloc();
return rc;
}
//-----------------------------------------------------------------------------
//
// Function: BSPClockGetFreq
//
// Retrieves the clock frequency in Hz for the specified clock signal.
//
// Parameters:
// sig
// [in] Clock signal.
// freq
// [out] Current frequency in Hz.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL BSPClockGetFreq(DDK_CLOCK_SIGNAL sig, UINT32 *freq)
{
*freq = g_pBspArgs->clockFreq[sig];
return TRUE;
}
//-----------------------------------------------------------------------------
//
// Function: BSPClockUpdateFreq
//
// Updates the clock frequency in Hz for the specified clock signal.
//
// Parameters:
// sig
// [in] Clock signal.
// src
// [in] Selects the input clock source.
// preDiv
// [in] Specifies the value programmed into the baud clock predivider.
// postDiv
// [in] Specifies the value programmed into the baud clock postdivider.
//
// Returns:
// Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL BSPClockUpdateFreq(DDK_CLOCK_SIGNAL sig, DDK_CLOCK_BAUD_SOURCE src,
UINT32 div)
{
UINT32 srcFreq;
switch (src) {
case DDK_CLOCK_BAUD_SOURCE_MPLL:
srcFreq = g_pBspArgs->clockFreq[DDK_CLOCK_SIGNAL_MPLL];
break;
case DDK_CLOCK_BAUD_SOURCE_SPLL:
srcFreq = g_pBspArgs->clockFreq[DDK_CLOCK_SIGNAL_SPLL];
break;
}
switch (sig) {
case DDK_CLOCK_SIGNAL_SSI1:
case DDK_CLOCK_SIGNAL_SSI2:
case DDK_CLOCK_SIGNAL_H264:
g_pBspArgs->clockFreq[sig] = srcFreq / (div >> 1);
break;
default:
g_pBspArgs->clockFreq[sig] = srcFreq / (div + 1);
}
return TRUE;
}
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