bspserial.c

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT 
//
//-----------------------------------------------------------------------------
//
//  File:  bspserial.c
//
//  Provides BSP-specific configuration routines for the UART peripheral.
//
//-----------------------------------------------------------------------------


//------------------------------------------------------------------------------
// INCLUDE FILES  
//------------------------------------------------------------------------------

#include <windows.h>
#include <bsp.h>
#include <uart.h>



//------------------------------------------------------------------------------
// MACRO DEFINITIONS 
//------------------------------------------------------------------------------
//#define UART_CLK                BSP_PERCLK1_FREQ
#define UART_MAX_DIV            7


//------------------------------------------------------------------------------
// Local Functions
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
//
// Function: BSPUartCalRFDIV
//
// This is a private function to calculate the data
// rate divider from input frequency.
//
// Parameters:
//      dwFrequency
//          [in] Frequency requested.
//
// Returns:
//      Data rate divisor for requested frequency.
//-----------------------------------------------------------------------------
UCHAR BSPUartCalRFDIV( ULONG* pRefFreq )
{
    UCHAR dwDivisor; // the data rate divisor
	UINT32 freq;

    DDKClockGetFreq(DDK_CLOCK_SIGNAL_PERDIV1, &freq);

    dwDivisor =(UCHAR) (freq / *pRefFreq);

    if (dwDivisor == 0)
        dwDivisor = 1;
    else if (dwDivisor > UART_MAX_DIV)
        dwDivisor = UART_MAX_DIV;

    *pRefFreq = freq /dwDivisor;

    return dwDivisor;
}


//-----------------------------------------------------------------------------
//
// Function: BSPUartGetType
//
// This is a private function to get the UART type with specified Uart IO address.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//
// Returns:
//      corresponding uart type.
//-----------------------------------------------------------------------------
BOOL BSPUartGetType(ULONG HWAddr, uartType_c * pType)
{
    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
            *pType=DCE;
            return TRUE;
        case CSP_BASE_REG_PA_UART2:
            *pType=DCE;
            return TRUE;
        case CSP_BASE_REG_PA_UART3:
            *pType=DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART4:
            *pType=DTE;				
            return TRUE;
        case CSP_BASE_REG_PA_UART5:	
            *pType=DTE;
            return TRUE;
        case CSP_BASE_REG_PA_UART6:
            *pType=DTE;
            return TRUE;
        default:
            return FALSE;
    }
}


//-----------------------------------------------------------------------------
//
// Function: BSPUartEnableClock
//
// This function is to enable/disable UART clock.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bEnable
//          [in] TRUE if Uart Clock is to be enabled. FALSE if Uart Clock is
//                to be disabled.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPUartEnableClock(ULONG HWAddr, BOOL bEnable)
{
    BOOL result = FALSE;
	DDK_CLOCK_GATE_INDEX cgIndex;

    switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART1;
            break;
        case CSP_BASE_REG_PA_UART2:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART2;
            break;
        case CSP_BASE_REG_PA_UART3:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART3;
            break;
        case CSP_BASE_REG_PA_UART4:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART4;
            break;
        case CSP_BASE_REG_PA_UART5:			
            cgIndex=DDK_CLOCK_GATE_INDEX_UART5;
            break;
        case CSP_BASE_REG_PA_UART6:
            cgIndex=DDK_CLOCK_GATE_INDEX_UART6;
            break;
        default:
            return result;
    }

    if (bEnable)
        result = DDKClockSetGatingMode(cgIndex, DDK_CLOCK_GATE_MODE_ENABLE);
    else
        result = DDKClockSetGatingMode(cgIndex, DDK_CLOCK_GATE_MODE_DISABLE);

    return result;
}

//-----------------------------------------------------------------------------
//
// Function: BSPUartConfigGPIO
//
// This function is to configures UART GPIO pins.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//      bIR
//          [in] TRUE if SIR. FALSE if not SIR.
//      bEnable
//          [in] TRUE if enable Uart GPIO pins. FALSE if disable Uart
//                GPIO pins.
//
// Returns:
//      TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPUartConfigGPIO(ULONG HWAddr, BOOL bIR, BOOL bEnable)
{
    BOOL result = FALSE;
    DDK_GPIO_CFG  cfg;

    if (bIR) {
        switch (HWAddr) {
            case CSP_BASE_REG_PA_UART1:
                DDK_GPIO_SET_CONFIG(cfg, UART1_IR);
                break;
            case CSP_BASE_REG_PA_UART2:
                DDK_GPIO_SET_CONFIG(cfg, UART2_IR);
                break;
            case CSP_BASE_REG_PA_UART3:
                DDK_GPIO_SET_CONFIG(cfg, UART3_IR);
                break;
            case CSP_BASE_REG_PA_UART4:
                DDK_GPIO_SET_CONFIG(cfg, UART4_IR);
                break;
            case CSP_BASE_REG_PA_UART5:
                DDK_GPIO_SET_CONFIG(cfg, UART5_IR);
                break;
            case CSP_BASE_REG_PA_UART6:
                DDK_GPIO_SET_CONFIG(cfg, UART6_IR);
                break;
            default:
                return result;
        }
    }
    else {
        switch (HWAddr) {
            case CSP_BASE_REG_PA_UART1:
                DDK_GPIO_SET_CONFIG(cfg, UART1);
                break;
            case CSP_BASE_REG_PA_UART2:
                DDK_GPIO_SET_CONFIG(cfg, UART2);
                break;
            case CSP_BASE_REG_PA_UART3:
                DDK_GPIO_SET_CONFIG(cfg, UART3);
                break;
            case CSP_BASE_REG_PA_UART4:
                DDK_GPIO_SET_CONFIG(cfg, UART4_ALT);
                break;
            case CSP_BASE_REG_PA_UART5:
                DDK_GPIO_SET_CONFIG(cfg, UART5_ALT);
                break;
            case CSP_BASE_REG_PA_UART6:
                DDK_GPIO_SET_CONFIG(cfg, UART6_ALT);
                break;
            default:
                return result;
        }
    }

    if (bEnable)
    {
        if(DDKGpioEnable(&cfg) == FALSE) {
            ERRORMSG(1, (TEXT("Cannot enable UART gpio!\r\n")));
            goto CleanUp;
        }

    }
    else {
        if(DDKGpioDisable(&cfg) == FALSE) {
            ERRORMSG (1, (TEXT("Cannot Disable UART gpio!\r\n"))); 
            goto CleanUp;
        }

    }

    result = TRUE;

CleanUp:
    return result;
}


//-----------------------------------------------------------------------------
//
// Function: BSPUartGetPort
//
// Returns the port corresponding to a UART.
//
// Parameters:
//      HWAddr
//          [in] Physical IO address.
//
// Returns:
//      
//-----------------------------------------------------------------------------
#ifdef DSR_ENABLE

BOOL BSPUartGetPort(ULONG HWAddr, UartPort * pPort)
{
    BOOL Retval = FALSE;
	switch (HWAddr) {
        case CSP_BASE_REG_PA_UART1:
        case CSP_BASE_REG_PA_UART2:
			*pPort = UARTA;			
			Retval = TRUE;
			break;

        case CSP_BASE_REG_PA_UART4:
        case CSP_BASE_REG_PA_UART3: // MX27 UARTB mapped to UART3
			*pPort = UARTB;
			Retval = TRUE;
			break;

		default:
            break;
    }

	return RetVal;
}

#endif