fs453.cpp

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

    rc = Fs453WriteRegister(FS453_CR, &data);
    if(rc != TRUE)
    {
        goto failed;
    }
  
    return TRUE;
failed:
    return FALSE;
}

//-----------------------------------------------------------------------------
//
//  Function: m_fs453UpdatePLL
//
//  This function updates internal pll setting.
//
//  Parameters:
//      None.
//
//  Returns:
//      Returns TRUE if successful, otherwise returns FALSE.
//
//-----------------------------------------------------------------------------
BOOL m_fs453UpdatePLL(void)
{
    DWORD data;
    BOOL rc = FALSE;
  
    data = ( m_dwFs453CrVal |
        CSP_BITFVAL(FS453_CR_NCO_EN, FS453_SET_ENABLE) );
  
    rc = Fs453WriteRegister(FS453_CR, &data);
    if(rc != TRUE)
    {
        goto failed;
    }
  
    data &= ~CSP_BITFMASK(FS453_CR_NCO_EN);
    data |= CSP_BITFVAL(FS453_CR_NCO_EN, FS453_SET_DISABLE);
  
    rc = Fs453WriteRegister(FS453_CR, &data);
    if(rc != TRUE)
    {
        goto failed;
    }
  
    return TRUE;
failed:
    return FALSE;
}

BOOL Fs453Configure(TVIN_COLOR color, TVOUT_MODE mode)
{
    BOOL  rc = FALSE;
    DWORD data;
    BOOL   bOutUnderscan = FS453_UNDERSCAN_TVIMAGE_BOOL;
    RETAILMSG (0, (TEXT("Fs453Configure TVIN_COLOR color 0x%x TVOUT_MODE mode 0x%x\r\n"), color, mode) );
    //  color = TVIN_COLOR_RGB;
    //  mode = TVOUT_MODE_PAL;

    FS453PARAM * pFs453Param = m_Fs453Parameters[mode];
  
    // ------------------------------------------------------------------------
    // ------ Basic Init
    // 1. Clear NCO_EN and SRESET
    if(mode == TVOUT_MODE_PAL)
    {
        m_dwFs453CrVal = ( CSP_BITFVAL(FS453_CR_GCC_CK_LVL, FS453_CR_GCC_CK_LVL_LOW_VOL) |
                 CSP_BITFVAL(FS453_CR_PAL_NTSCIN, FS453_SET_ENABLE) );
  
    }
    else
    {
        m_dwFs453CrVal = ( CSP_BITFVAL(FS453_CR_GCC_CK_LVL, FS453_CR_GCC_CK_LVL_LOW_VOL) );
  
    }

    data = ( m_dwFs453CrVal  |
        CSP_BITFVAL(FS453_CR_NCO_EN, FS453_SET_DISABLE) |
        CSP_BITFVAL(FS453_CR_SRESET, FS453_SET_DISABLE));
  
    Fs453WriteRegister(FS453_CR, &data); //0x2000

    // 3. QPR
    data = (CSP_BITFVAL(FS453_QPR_INITIATE, FS453_QPR_SET_INITIATE) |
        CSP_BITFVAL(FS453_QPR_QK_UIM,   FS453_QPR_QK_UIM_NATIONAL) |
        CSP_BITFVAL(FS453_QPR_QK_OS,  FS453_QPR_QK_OS_SDTV) |
        CSP_BITFVAL(FS453_QPR_QK_FF,  FS453_SET_ENABLE) |     // Flicker Fileter
        CSP_BITFVAL(FS453_QPR_QK_OM,  FS453_QPR_QK_OM_SVIDEO_COMPOSITE) |
        CSP_BITFVAL(FS453_QPR_QK_GMODE, FS453_QPR_QK_GMODE_VGA));

    if(mode == TVOUT_MODE_PAL)
    {
        data |= CSP_BITFVAL(FS453_QPR_QK_PN, FS453_QPR_QK_PN_PAL);
    }
    else
    {
        data |= CSP_BITFVAL(FS453_QPR_QK_PN, FS453_QPR_QK_PN_NTSC);
  
    }

    if(color == TVIN_COLOR_YCRCB)
    {
        data |= CSP_BITFVAL(FS453_QPR_QK_YC_IN, FS453_QPR_QK_YC_IN_YCRCB);
    }
    else
    {
        data |= CSP_BITFVAL(FS453_QPR_QK_YC_IN, FS453_QPR_QK_YC_IN_RGB);
    }

    if(bOutUnderscan)
    {
        // Underscan
        data |= CSP_BITFVAL(FS453_QPR_QK_UO, FS453_QPR_QK_UO_UNDERSCAN);
    }
    else
    {
        // Overscan
        data |= CSP_BITFVAL(FS453_QPR_QK_UO, FS453_QPR_QK_UO_OVERSCAN);
    }

    Fs453WriteRegister(FS453_QPR, &data); //0x9C40

    // 4. PWR_MGNT - SDTV Clock On/ DAC output ON
    data = ( CSP_BITFVAL(FS453_PWR_MGNT_GTLIO_PD,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_PLL_PD,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_CLKOFF,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_CLK_SOFF,   FS453_PWR_MGNT_CLK_SOFF_HDTV_CLK_OFF) | //SDTV Clock On
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_LP,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_LP,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_LP,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_LP,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_BGAP_OFF,   FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_D_OFF,  FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_C_OFF,  FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_B_OFF,  FS453_SET_DISABLE) |
       CSP_BITFVAL(FS453_PWR_MGNT_DAC_A_OFF,  FS453_SET_DISABLE) );

    rc = Fs453WriteRegister(FS453_PWR_MGNT, &data); //0x200

    // 2. Issue a SRESET
    m_fs453SwReset();

    // ------------------------------------------------------------------------
    // ------ Set scale and position factors
    // 5. position

    data =  CSP_BITFVAL(FS453_IHO_IHO, pFs453Param[FS453_PARAM_POSITION_HORIZ]);
  
    Fs453WriteRegister(FS453_IHO, &data); //0x40
  
    data =  CSP_BITFVAL(FS453_IVO_IVO, pFs453Param[FS453_PARAM_POSITION_VERTI]);
  
    Fs453WriteRegister(FS453_IVO, &data); //0x18
  
    data =  CSP_BITFVAL(FS453_IHW_IHW, pFs453Param[FS453_PARAM_HACTIVE]);
  
    Fs453WriteRegister(FS453_IHW, &data); //0x280

    // 6. scale
    data =  CSP_BITFVAL(FS453_VSC_VSC, pFs453Param[FS453_PARAM_SCALE_VERTI]);
  
    Fs453WriteRegister(FS453_VSC, &data); //0x276
  
    data = (CSP_BITFVAL(FS453_HSC_HUSC, pFs453Param[FS453_PARAM_SCALE_HORIZ_UPSCALE])|
        CSP_BITFVAL(FS453_HSC_HDSC, pFs453Param[FS453_PARAM_SCALE_HORIZ_DOWNSCALE]));
  
    Fs453WriteRegister(FS453_HSC, &data); //0x1000
  
    // 7. bypass
    data = (CSP_BITFVAL(FS453_BYPASS_CAC_BYPASS, FS453_SET_ENABLE)|
        CSP_BITFVAL(FS453_BYPASS_HDS_BYPASS, FS453_SET_ENABLE));
  
    Fs453WriteRegister(FS453_BYPASS, &data); //0x000A for NTSC - not using horizon down scale
  
    // 13. FIFO
    data = CSP_BITFVAL(FS453_FIFO_LAT_FIFO_LAT, pFs453Param[FS453_PARAM_FIFO_LATENCY]);
  
    Fs453WriteRegister(FS453_FIFO_LAT, &data); //0x00a4 for NTSC

    // ------------------------------------------------------------------------
    // ------ Set PLL Register
    // 9. clock
    // ... Set NCONL
    data = CSP_BITFVAL(FS453_NCONL_NCONL, pFs453Param[FS453_PARAM_PLL_NCONL]);
  
    Fs453WriteRegister(FS453_NCONL, &data); //0x0000
  
    // ... Set NCONH
    data = CSP_BITFVAL(FS453_NCONH_NCONH, pFs453Param[FS453_PARAM_PLL_NCONH]);
  
    Fs453WriteRegister(FS453_NCONH, &data); //0x0000
  
    // ... Set NCODL
    data = CSP_BITFVAL(FS453_NCODL_NCODL, pFs453Param[FS453_PARAM_PLL_NCODL]);
  
    Fs453WriteRegister(FS453_NCODL, &data); //0x0000
  
    // ... Set NCODH
    data = CSP_BITFVAL(FS453_NCODH_NCODH, pFs453Param[FS453_PARAM_PLL_NCODH]);
  
    Fs453WriteRegister(FS453_NCODH, &data); //0x0000
  
    // ... Set PLLM
    data = CSP_BITFVAL(FS453_PLLM_PUMPCNTL_PLLM, pFs453Param[FS453_PARAM_PLL_M]);
  
    Fs453WriteRegister(FS453_PLLM_PUMPCNTL, &data); //0x30f7

    // ... Set PLLN
    data = CSP_BITFVAL(FS453_PLLN_PLLN, pFs453Param[FS453_PARAM_PLL_N]);
  
    Fs453WriteRegister(FS453_PLLN, &data); //0x2c
  
    // ... Set PLLP
    data = (CSP_BITFVAL(FS453_PLL_POSTDIV_PLL_EP, pFs453Param[FS453_PARAM_PLL_P_EP])|
        CSP_BITFVAL(FS453_PLL_POSTDIV_PLL_IP, pFs453Param[FS453_PARAM_PLL_P_IP]));
  
    Fs453WriteRegister(FS453_PLL_POSTDIV, &data); //0x0505
  
  
    // ------------------------------------------------------------------------
    // ------ Set UIM mode
    /*
    data = (CSP_BITFVAL(FS453_MISC_P_ORDER, FS453_SET_DISABLE)| // Only affects UIM is 11,12
        CSP_BITFVAL(FS453_MISC_BRDG_RST,FS453_SET_DISABLE)| // Bridge pointer reset - disable
        CSP_BITFVAL(FS453_MISC_UIM_E,   FS453_SET_DISABLE)| // Change state at edge(0), at middle of pix(1)
        CSP_BITFVAL(FS453_MISC_UV_SWAP, FS453_SET_ENABLE)| // Swap Cr(V) and Cb(U) internal input
        CSP_BITFVAL(FS453_MISC_UIM_DEC, FS453_SET_DISABLE)| //horizontal prescaler divide by 2 to support high resolution VGA mode.
        CSP_BITFVAL(FS453_MISC_UIM_CCLK,FS453_SET_DISABLE)| //inverts the edge on which input control is latched.
        CSP_BITFVAL(FS453_MISC_UIM_DCLK,FS453_SET_DISABLE)| //inverts the edge on which input data is latched.
        CSP_BITFVAL(FS453_MISC_UIM_MOD, FS453_MISC_UIM_MOD_N565));
  
    Fs453WriteRegister(FS453_MISC, &data);
    */

    // ------------------------------------------------------------------------
    // ------ Set Video mode
    // ...FS453 Video Output Modes
    //
    //    VIDEO OUTPUT MODE   | VID_MODE | EncMod | *MB | Sg0 | Sg1 | Sg2 | Sg3
    //    -----------------------------------------------------------------------
    //    Composite & S-Video |    0     | Normal |  -  |  Y  |  C  | GND | CVBS
    //    SDTV YPrPb      |    1     | YUV    |  -  |  Y  |  Pr |  Pb | CVBS
    //    SCART         |    1     | Normal |  -  | GRN |  R  | BLU | CVBS
    //    HDTV YPrPb      |    2     |   --   |  0  |  Y  |  Pr |  Pb | GND
    //    VGA RGB       |    2     |   --   |  1  | GRN | RED | BLU | GND
    //
    //    *MB: Matrix Bypasses
  
    // 10. VID_CNTL0
      data = (CSP_BITFVAL(FS453_VID_CNTL0_TOP_FIELD,  FS453_VID_CNTL0_TOP_FIELD_IS_LINE1)| // Selects the Interlaced HDTV Top Field.
        CSP_BITFVAL(FS453_VID_CNTL0_OBIN_USIG,  FS453_VID_CNTL0_OBIN_USIG_UNSIGNED)| // Input data in the YCrCb offset binary format, or in the RGB unsigned format.
        CSP_BITFVAL(FS453_VID_CNTL0_PRPB_SYNC,  FS453_SET_DISABLE)| // Inserts syncs on NOT ONLY Y, BUT Pr, and Pb components
        CSP_BITFVAL(FS453_VID_CNTL0_VSYNC5_6,   FS453_VID_CNTL0_VSYNC5_6_6HALF_LINES)|
        CSP_BITFVAL(FS453_VID_CNTL0_BLANK_INV,  FS453_SET_DISABLE)| // Disable - low active
        CSP_BITFVAL(FS453_VID_CNTL0_FIELD_INV,  FS453_SET_DISABLE)| // Disable - use if FIELD_MS is set to 0
        CSP_BITFVAL(FS453_VID_CNTL0_VSYNC_INV,  FS453_SET_ENABLE)| // Enable - input Vertical timing is measured with respect the failing edge of VSync
        CSP_BITFVAL(FS453_VID_CNTL0_HSYNC_INV,  FS453_SET_ENABLE)| // Enable - input Horizontal timing is measured with respect the failing edge of HSync
        CSP_BITFVAL(FS453_VID_CNTL0_INT_PROG, FS453_SET_DISABLE)| // Disable - input image is NOT interlaced.
        CSP_BITFVAL(FS453_VID_CNTL0_FIELD_MS, FS453_SET_ENABLE)| // Normally set to 0 for HDTV modes or 1 for SDTV modes
        CSP_BITFVAL(FS453_VID_CNTL0_SYNC_LVL, FS453_SET_DISABLE)| // When set =1, HDTV sync amplitude is 300 mV, otherwise amplitude is 286 mV
        CSP_BITFVAL(FS453_VID_CNTL0_SYNC_BI_TRI,FS453_SET_DISABLE)| // When set =1, inserts Bi-level HDTV syncs, otherwise inserts Tri-level syncs.
        CSP_BITFVAL(FS453_VID_CNTL0_SYNC_ADD, FS453_SET_DISABLE)| // When set =1, inserts HDTV syncs.
        CSP_BITFVAL(FS453_VID_CNTL0_MATRIX_BYP, FS453_SET_DISABLE)| // When set =1, bypasses RGB to YUV matrix
        CSP_BITFVAL(FS453_VID_CNTL0_VID_MODE,   FS453_VID_CNTL0_VID_MODE_COMPOSIT_SVIDEO)); // see above

    Fs453WriteRegister(FS453_VID_CNTL0, &data); //0xb40//0x340
  
    // 11. latch clock
    // ... update fs453 internal pll
    m_fs453UpdatePLL();
  
    // 14. other misc
    // ------------------------------------------------------------------------
    // ------ PLL
    // ------------------------------------------------------------------------
    // ------ Set flicker filter
    // ... sharpness
    data = CSP_BITFVAL(FS453_SHP_SHP, 0x0008); // off
  
    Fs453WriteRegister(FS453_SHP, &data); //0x0008
  
    // ... flicker
    data = CSP_BITFVAL(FS453_FLK_FLK, 0x000C); // off
  
    Fs453WriteRegister(FS453_FLK, &data); //0x000c

    // ------------------------------------------------------------------------
    // ------ Set luma/chroma filter
    // ... Set Luma(Y) Notch
    data = (CSP_BITFVAL(FS453_MISC_8D_NOTCH_EN, FS453_SET_DISABLE) | //Y Notch filter - off
        CSP_BITFVAL(FS453_MISC_8D_NOTCH_WD, 0) | // 0 - narrow
        CSP_BITFVAL(FS453_MISC_8D_NOTCH_FREQ, 0)); // 2 - NTSC, 5 - PAL
  
    Fs453WriteRegister(FS453_MISC_8D, &data);
  
    data = (CSP_BITFVAL(FS453_MISC_47_CHR_BW,   FS453_FILTER_BANDWIDTH_NARROW) |
        CSP_BITFVAL(FS453_MISC_47_COMP_YUV, FS453_MISC_47_COMP_YUV_YUV_OUTPUT) | // YUV out
        CSP_BITFVAL(FS453_MISC_47_COMP_GAIN,FS453_MISC_47_COMP_GAIN_100));