📄 xldr.s
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;------------------------------------------------------------------------------
;
; Copyright (C) 2006-2007, Freescale Semiconductor, Inc. All Rights Reserved.
; THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
; AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
;
;------------------------------------------------------------------------------
;
; FILE: xldr.s
;
; Provides support for booting from a NAND device connected to the
; NAND flash controller.
;
;------------------------------------------------------------------------------
INCLUDE armmacros.s
INCLUDE mx27_base_regs.inc
INCLUDE mx27_base_mem.inc
INCLUDE image_cfg.inc
INCLUDE nandchip.inc
;-------------------------------------------------------------------------------
; ARM constants
;-------------------------------------------------------------------------------
ARM_CPSR_PRECISE EQU (1 << 8)
ARM_CPSR_IRQDISABLE EQU (1 << 7)
ARM_CPSR_FIQDISABLE EQU (1 << 6)
ARM_CPSR_MODE_SVC EQU 0x13
ARM_CTRL_ICACHE EQU (1 << 12)
ARM_CTRL_DCACHE EQU (1 << 2)
ARM_CTRL_MMU EQU (1 << 0)
ARM_CTRL_VECTORS EQU (1 << 13)
ARM_CACR_FULL EQU 0x3
;-------------------------------------------------------------------------------
; AIPI constants
;-------------------------------------------------------------------------------
AIPI_PSR0_OFFSET EQU 0x0000
AIPI_PSR1_OFFSET EQU 0x0004
AIPI_PAR_OFFSET EQU 0x0008
AIPI_AAOR_OFFSET EQU 0x000C
;-------------------------------------------------------------------------------
; PLLCRC constants
;-------------------------------------------------------------------------------
PLLCRC_CSCR_OFFSET EQU 0x0000
PLLCRC_MPCTL0_OFFSET EQU 0x0004
PLLCRC_MPCTL1_OFFSET EQU 0x0008
PLLCRC_SPCTL0_OFFSET EQU 0x000C
PLLCRC_SPCTL1_OFFSET EQU 0x0010
PLLCRC_OSC26MCTL_OFFSET EQU 0x0014
PLLCRC_PCDR0_OFFSET EQU 0x0018
PLLCRC_PCDR1_OFFSET EQU 0x001C
PLLCRC_PCCR0_OFFSET EQU 0x0020
PLLCRC_PCCR1_OFFSET EQU 0x0024
; Clock control register settings (FCLK/HCLK = 266MHz/133MHz)
IF BSP_OSC_32K
; 32K oscillator can be either 32000 Hz or 32768 Hz
IF REF_32KHZ_32000
; the 32.000k oscillator is used
IF MX27TO2
PLLCRC_MPCTL0_SETTING EQU 0x00211803 ; 398998000 Hz
PLLCRC_CSCR_SETTING EQU 0x332C010F
PLLCRC_PCDR0_SETTING EQU 0x701C024B
ELSE
; it is a TO1 processor
PLLCRC_MPCTL0_SETTING EQU 0x04C22017 ; 266008944 Hz
PLLCRC_CSCR_SETTING EQU 0x332F030F
PLLCRC_PCDR0_SETTING EQU 0x8020134B
ENDIF
PLLCRC_SPCTL0_SETTING EQU 0x04FF1C53
ELSE ; not 32000 Hz
; 32K clock, not 32000 Hz
IF REF_32KHZ_32768
IF MX27TO2
PLLCRC_MPCTL0_SETTING EQU 0x01EF15D5 ; 399000080 Hz
PLLCRC_CSCR_SETTING EQU 0x332C010F
PLLCRC_PCDR0_SETTING EQU 0x701C024B
ELSE
; it is a TO1 processor
PLLCRC_MPCTL0_SETTING EQU 0x0C3D30EF ; 266000054 Hz
PLLCRC_CSCR_SETTING EQU 0x332F030F
PLLCRC_PCDR0_SETTING EQU 0x8020134B
ENDIF
PLLCRC_SPCTL0_SETTING EQU 0x043A1C09
ENDIF
; if the 32k clock is not 32000 Hz and not 32768 Hz then other
; values must be defined here.
ENDIF ; REF_32KHZ_32000
ELSE
; 26M crystal is used
IF BSP_TVOUT
; in TV-out config, crystal is actually 27M
IF MX27TO2
PLLCRC_MPCTL0_SETTING EQU 0x010D1C6C
ELSE
PLLCRC_MPCTL0_SETTING EQU 0x050D24E6
ENDIF
PLLCRC_SPCTL0_SETTING EQU 0x041A2403
ELSE
; 26M crystal
IF MX27TO2
PLLCRC_MPCTL0_SETTING EQU 0x00331C23
ELSE
PLLCRC_MPCTL0_SETTING EQU 0x04152806
ENDIF
PLLCRC_SPCTL0_SETTING EQU 0x040C2403
ENDIF
IF MX27TO2
PLLCRC_CSCR_SETTING EQU 0x332F0107
PLLCRC_PCDR0_SETTING EQU 0x701C024B
ELSE
PLLCRC_CSCR_SETTING EQU 0x332F0307
PLLCRC_PCDR0_SETTING EQU 0x8020134B
ENDIF
ENDIF
PLLCRC_MPCTL1_LF_SETTING EQU 0x00008000
PLLCRC_SPCTL1_LF_SETTING EQU 0x00008000
PLLCRC_PCDR1_SETTING EQU 0x04070507
PLLCRC_PCCR0_SETTING EQU 0x12000000
PLLCRC_PCCR1_SETTING EQU 0x00580788
;-------------------------------------------------------------------------------
; SYSCTRL constants
;-------------------------------------------------------------------------------
SYSCTRL_DSCR1_OFFSET EQU 0x0020
SYSCTRL_DSCR2_OFFSET EQU 0x0024
SYSCTRL_DSCR3_OFFSET EQU 0x0028
SYSCTRL_DSCR4_OFFSET EQU 0x002C
SYSCTRL_DSCR5_OFFSET EQU 0x0030
SYSCTRL_DSCR6_OFFSET EQU 0x0034
SYSCTRL_DSCR7_OFFSET EQU 0x0038
SYSCTRL_DSCR8_OFFSET EQU 0x003C
SYSCTRL_DSCR9_OFFSET EQU 0x0040
SYSCTRL_DSCR10_OFFSET EQU 0x0044
SYSCTRL_DSCR11_OFFSET EQU 0x0048
SYSCTRL_DSCR12_OFFSET EQU 0x004C
SYSCTRL_DSCR13_OFFSET EQU 0x0050
; Driving strength setting for DDR
SYSCTRL_DSCR3_SETTING EQU 0x55555555
SYSCTRL_DSCR5_SETTING EQU 0x55555555
SYSCTRL_DSCR6_SETTING EQU 0x55555555
SYSCTRL_DSCR7_SETTING EQU 0x00005005
SYSCTRL_DSCR8_SETTING EQU 0x15555555
;-------------------------------------------------------------------------------
; ESDRAMC constants
;-------------------------------------------------------------------------------
ESDRAMC_ESDCTL0_OFFSET EQU 0x0000
ESDRAMC_ESDCFG0_OFFSET EQU 0x0004
ESDRAMC_ESDCTL1_OFFSET EQU 0x0008
ESDRAMC_ESDCFG1_OFFSET EQU 0x000C
ESDRAMC_ESDMISC_OFFSET EQU 0x0010
;-------------------------------------------------------------------------------
; NANDFC constants
;-------------------------------------------------------------------------------
NANDFC_MAIN_BUFF0_OFFSET EQU (0x0)
NANDFC_MAIN_BUFF1_OFFSET EQU (0x200)
NANDFC_MAIN_BUFF2_OFFSET EQU (0x400)
NANDFC_MAIN_BUFF3_OFFSET EQU (0x600)
NANDFC_SPARE_BUFF0_OFFSET EQU (0x800)
NANDFC_SPARE_BUFF1_OFFSET EQU (0x810)
NANDFC_SPARE_BUFF2_OFFSET EQU (0x820)
NANDFC_SPARE_BUFF3_OFFSET EQU (0x830)
NANDFC_NFC_BUFSIZE_OFFSET EQU (0xE00)
NANDFC_RAM_BUFF_ADDRESS_OFFSET EQU (0xE04)
NANDFC_NAND_FLASH_ADD_OFFSET EQU (0xE06)
NANDFC_NAND_FLASH_CMD_OFFSET EQU (0xE08)
NANDFC_NFC_CONFIGURATION_OFFSET EQU (0xE0A)
NANDFC_ECC_STATUS_RESULT_OFFSET EQU (0xE0C)
NANDFC_ECC_RSLT_MAIN_AREA_OFFSET EQU (0xE0E)
NANDFC_ECC_RSLT_SPARE_AREA_OFFSET EQU (0xE10)
NANDFC_NF_WR_PROT_OFFSET EQU (0xE12)
NANDFC_UNLOCK_START_BLK_ADD_OFFSET EQU (0xE14)
NANDFC_UNLOCK_END_BLK_ADD_OFFSET EQU (0xE16)
NANDFC_FLASH_WR_PR_ST_OFFSET EQU (0xE18)
NANDFC_NAND_FLASH_CONFIG1_OFFSET EQU (0xE1A)
NANDFC_NAND_FLASH_CONFIG2_OFFSET EQU (0xE1C)
NANDFC_CONFIG1_SP_EN EQU (1 << 2)
NANDFC_CONFIG1_NF_CE EQU (1 << 7)
NANDFC_CONFIG2_FCMD EQU (1 << 0)
NANDFC_CONFIG2_FADD EQU (1 << 1)
NANDFC_CONFIG2_FDI EQU (1 << 2)
NANDFC_CONFIG2_FDO_PAGE EQU (1 << 3)
NANDFC_CONFIG2_FDO_ID EQU (1 << 4)
NANDFC_CONFIG2_FDO_STATUS EQU (1 << 5)
NANDFC_CONFIG2_INT EQU (1 << 15)
OPT 2 ; disable listing
INCLUDE kxarm.h
OPT 1 ; reenable listing
TEXTAREA
; romimage needs pTOC. give it one.
pTOC DCD -1
EXPORT pTOC
;-------------------------------------------------------------------------------
;
; Function: StartUp
;
; System bootstrap function.
;
; Parameters:
; None.
;
; RETURNS:
; None.
;
;-------------------------------------------------------------------------------
STARTUPTEXT
LEAF_ENTRY StartUp
; Wait for bootload complete
ldr r1, =(CSP_BASE_REG_PA_NANDFC+NANDFC_NAND_FLASH_CONFIG2_OFFSET)
wait_Bootloop
ldrh r0, [r1]
ands r0, r0, #NANDFC_CONFIG2_INT
beq wait_Bootloop
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Put the processor in supervisor mode
; Disable the interrupt request (IRQ) and fast interrupt request (FIQ)
; inputs
;--------------------------------------------------------------------------
mrs r0, cpsr ; r0 = CPSR
mov r0, #ARM_CPSR_MODE_SVC ; enter supervisor mode
orr r0, r0, #ARM_CPSR_IRQDISABLE ; disable normal IRQ
orr r0, r0, #ARM_CPSR_FIQDISABLE ; disable fast IRQ
msr cpsr_c, r0 ; update CPSR control bits
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Disable memory management unit (MMU) and both the instruction and data
; caches
;--------------------------------------------------------------------------
mrc p15, 0, r0, c1, c0, 0 ; r0 = system control reg
bic r0, r0, #ARM_CTRL_ICACHE ; disable ICache
bic r0, r0, #ARM_CTRL_DCACHE ; disable DCache
bic r0, r0, #ARM_CTRL_MMU ; disable MMU
bic r0, r0, #ARM_CTRL_VECTORS ; set vector base to 0x00000000
mcr p15, 0, r0, c1, c0, 0 ; update system control reg
;
; Set up AIPI registers for module access.
; PSR[1:0]: 10 = 32bit, 01 = 16bit, 00 = 8bit.
; PAR: 1 = Supervisor access only, 0 = Access rights is up to peripheral.
; AAOR: 1 = Atomic access only, 0 = Accept non-atomic access.
;
; AIPI1 settings:
; PSR[0]: 0x20040304
; PSR[1]: 0xDFFBFCFB (16-bit: WDOG, KPP, OWIRE, I2C)
; PAR: 0x00000001
; AAOR: 0x00000001 (reset value)
;
ldr r1, =CSP_BASE_REG_PA_AIPI1
ldr r0, =0x20040304
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xDFFBFCFB
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_PAR_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_AAOR_OFFSET]
;
; AIPI2 settings:
; PSR[0]: 0x07FFC200
; PSR[1]: 0xFFFFFFFF
; PAR: 0xF8003D01
; AAOR: 0x00000001 (reset value)
;
ldr r1, =CSP_BASE_REG_PA_AIPI2
ldr r0, =0x07FFC200
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xFFFFFFFF
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0xF8003D01
str r0, [r1, #AIPI_PAR_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_AAOR_OFFSET]
;
; Set up PLLCRC
;
ldr r0, =CSP_BASE_REG_PA_CRM
ldr r1, =PLLCRC_PCDR0_SETTING
str r1, [r0, #PLLCRC_PCDR0_OFFSET]
ldr r1, =PLLCRC_PCDR1_SETTING
str r1, [r0, #PLLCRC_PCDR1_OFFSET]
ldr r1, =PLLCRC_MPCTL0_SETTING
str r1, [r0, #PLLCRC_MPCTL0_OFFSET]
ldr r1, =PLLCRC_SPCTL0_SETTING
str r1, [r0, #PLLCRC_SPCTL0_OFFSET]
ldr r1, =PLLCRC_CSCR_SETTING
str r1, [r0, #PLLCRC_CSCR_OFFSET]
; Wait for PLL lock
WaitForMPLL
ldr r1, [r0, #PLLCRC_MPCTL1_OFFSET]
tst r1, #PLLCRC_MPCTL1_LF_SETTING
beq WaitForMPLL
WaitForSPLL
ldr r1, [r0, #PLLCRC_SPCTL1_OFFSET]
tst r1, #PLLCRC_SPCTL1_LF_SETTING
beq WaitForSPLL
ldr r1, =PLLCRC_PCCR0_SETTING
str r1, [r0, #PLLCRC_PCCR0_OFFSET]
ldr r1, =PLLCRC_PCCR1_SETTING
str r1, [r0, #PLLCRC_PCCR1_OFFSET]
;
; Set up SYSCTRL for DDR
;
ldr r0, =CSP_BASE_REG_PA_SYSCTRL
ldr r1, =SYSCTRL_DSCR3_SETTING
str r1, [r0, #SYSCTRL_DSCR3_OFFSET]
ldr r1, =SYSCTRL_DSCR5_SETTING
str r1, [r0, #SYSCTRL_DSCR5_OFFSET]
ldr r1, =SYSCTRL_DSCR6_SETTING
str r1, [r0, #SYSCTRL_DSCR6_OFFSET]
ldr r1, =SYSCTRL_DSCR7_SETTING
str r1, [r0, #SYSCTRL_DSCR7_OFFSET]
ldr r1, =SYSCTRL_DSCR8_SETTING
str r1, [r0, #SYSCTRL_DSCR8_OFFSET]
;
; Set up ESDRAMC for DDR
;
ldr r1, =CSP_BASE_REG_PA_ESDRAMC
ldr r2, =IMAGE_BOOT_RAM_PA_START
; LPDDR delay line soft reset
ldr r0, =0x00000008
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Enable DDR operation
ldr r0, =0x00000004
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Set DDR timing parameters
ldr r0, =0x00795429
str r0, [r1, #ESDRAMC_ESDCFG0_OFFSET]
; Set precharge command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Precharge command (1 << 28) = 0x10000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x92200000
ldr r0, =0x92200000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Access SDRAM with A10 high to precharge all banks
; Address used for mode, data ignored
ldr r0, =0x0
str r0, [r2, #0xF00]
; Set autorefresh command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Autorefresh command (2 << 28) = 0x20000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xA2200000
ldr r0, =0xA2200000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Use writes to refresh all banks of SDRAM
; Address used for mode, data ignored
ldr r0, =0x0
str r0, [r2]
str r0, [r2]
; Set load mode command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Load mode command (3 << 28) = 0x30000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xB2200000
ldr r0, =0xB2200000
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