📄 pbc.h
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//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// Header: pbc.h
//
// Provides definitions for the Peripheral Bus Control (PBC) module of the
// ADS main board. The PBC is implented using a CPLD.
//
//------------------------------------------------------------------------------
#ifndef __PBC_H__
#define __PBC_H__
#if __cplusplus
extern "C" {
#endif
//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
UINT16 VERSION;
UINT16 _pad1[3];
UINT16 BCTRL1_SET;
UINT16 _pad2;
UINT16 BCTRL1_CLEAR;
UINT16 _pad3;
UINT16 BCTRL2_SET;
UINT16 _pad4;
UINT16 BCTRL2_CLEAR;
UINT16 _pad5;
UINT16 BCTRL3_SET;
UINT16 _pad6;
UINT16 BCTRL3_CLEAR;
UINT16 _pad7;
UINT16 BCTRL4_SET;
UINT16 _pad8;
UINT16 BCTRL4_CLEAR;
UINT16 _pad9;
UINT16 BSTAT1;
UINT16 _pad10;
UINT16 INT_STATUS;
UINT16 _pad11;
UINT16 INT_CUR_STATUS;
UINT16 _pad12[3];
UINT16 INT_MASK_SET;
UINT16 _pad13;
UINT16 INT_MASK_CLEAR;
UINT16 _pad14;
} CSP_PBC_REGS, *PCSP_PBC_REGS;
//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
#define PBC_SC16C652_OFFSET 0x00020000
#define PBC_UART_STATUS_OFFSET 0x00022000
#define PBC_UART_CTRL_SET_OFFSET 0x00024000
#define PBC_UART_CTRL_CLEAR_OFFSET 0x00026000
#define PBC_CS8900_IOBASE_OFFSET 0x00040000
#define PBC_CS8900_MEMBASE_OFFSET 0x00042000
#define PBC_CS8900_DMABASE_OFFSET 0x00044000
//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
// Version Register
#define PBC_VERSION_BOARD_VERSION_LSH 0
// Board Control Register 1 Set/Clear Register
#define PBC_BCTRL1_ENET_RST_LSH 0
#define PBC_BCTRL1_XUART_RST_LSH 1
#define PBC_BCTRL1_FEC_RST_LSH 2
#define PBC_BCTRL1_ENET_SLEEP_LSH 4
#define PBC_BCTRL1_LED_1_LSH 5
#define PBC_BCTRL1_LED_2_LSH 6
#define PBC_BCTRL1_LCDON_LSH 11
// Board Control Register 2 Set/Clear Register
#define PBC_BCTRL2_VCC_EN_LSH 2
#define PBC_BCTRL2_VPP_EN_LSH 3
#define PBC_BCTRL2_ATA_FEC_EN_LSH 4
#define PBC_BCTRL2_ATA_FEC_SEL_LSH 5
#define PBC_BCTRL2_ATA_EN_LSH 6
#define PBC_BCTRL2_IRDA_MOD_LSH 7
#define PBC_BCTRL2_IRDA_EN_LSH 8
#define PCB_BCTRL2_CCTL1_0_LSH 9
#define PCB_BCTRL2_CCTL1_1_LSH 10
// Board Control Register 3 Set/Clear Register
#define PBC_BCTRL3_HSH_EN_LSH 5
#define PBC_BCTRL3_FSH_MODE_LSH 6
#define PBC_BCTRL3_OTG_HS_EN_LSH 7
#define PBC_BCTRL3_OTG_VBUS_EN_LSH 8
#define PBC_BCTRL3_FSH_VBUS_EN_LSH 9
#define PBC_BCTRL3_USB_OTG_ON_LSH 11
#define PBC_BCTRL3_USB_FSH_ON_LSH 12
// Board Control Register 4 Set/Clear Register
#define PBC_BCTRL4_REGEN_LSH 0
#define PBC_BCTRL4_USER_OFF_LSH 1
#define PBC_BCTRL4_VIB_EN_LSH 2
#define PBC_BCTRL4_PWRGT1_EN_LSH 3
#define PBC_BCTRL4_PWRGT2_EN_LSH 4
#define PBC_BCTRL4_STDBY_PRI_LSH 5
// Board Status Register 1
#define PBC_BSTAT1_PRI_INT_LSH 0
#define PBC_BSTAT1_USB_BYP_LSH 1
#define PBC_BSTAT1_ATA_IOCS16_LSH 2
#define PBC_BSTAT1_ATA_CBLID_LSH 3
#define PBC_BSTAT1_ATA_DASP_LSH 4
#define PBC_BSTAT1_PWR_RDY_LSH 5
#define PBC_BSTAT1_SD3_WP_LSH 8
#define PBC_BSTAT1_SD2_WP_LSH 9
#define PBC_BSTAT1_SD1_WP_LSH 10
#define PBC_BSTAT1_SD3_DET_LSH 11
#define PBC_BSTAT1_SD2_DET_LSH 12
#define PBC_BSTAT1_SD1_DET_LSH 13
#define PBC_BSTAT1_MS_DET_LSH 14
// Interrupt Status Register
#define PBC_INT_LOW_BAT_LSH 1
#define PBC_INT_OTG_FS_OVR_LSH 2
#define PBC_INT_FSH_OVR_LSH 3
#define PBC_INT_FEC_INT_LSH 7
#define PBC_INT_ENET_INT_LSH 8
#define PBC_INT_OTG_FS_INT_LSH 9
#define PBC_INT_XUART_INT_LSH 10
#define PBC_INT_CCTL1_2_LSH 11
// Interrupt Current Status Register
#define PBC_INT_CUR_LOW_BAT_LSH 1
#define PBC_INT_CUR_OTG_FS_OVR_LSH 1
#define PBC_INT_CUR_FSH_OVR_LSH 1
// Interrrupt Mask Register
#define PBC_INT_MASK_SD2_R_EN_LSH 0
#define PBC_INT_MASK_LOW_BAT_LSH 1
#define PBC_INT_MASK_OTG_FS_OVR_LSH 2
#define PBC_INT_MASK_FSH_OVR_LSH 3
#define PBC_INT_MASK_SD3_R_EN_LSH 4
#define PBC_INT_MASK_MS_R_EN_LSH 5
#define PBC_INT_MASK_SD1_R_EN_LSH 6
#define PBC_INT_MASK_FEC_INT_LSH 7
#define PBC_INT_MASK_ENET_INT_LSH 8
#define PBC_INT_MASK_OTG_FS_INT_LSH 9
#define PBC_INT_MASK_XUART_INT_LSH 10
#define PBC_INT_MASK_CCTL1_2_LSH 11
#define PBC_INT_MASK_SD2_EN_LSH 12
#define PBC_INT_MASK_SD3_EN_LSH 13
#define PBC_INT_MASK_MS_EN_LSH 14
#define PBC_INT_MASK_SD1_EN_LSH 15
// UART Control Set Register
#define PBC_UART_CTRL_SET_DCE_DCD_LSH 0
#define PBC_UART_CTRL_SET_DCE_DSR_LSH 1
#define PBC_UART_CTRL_SET_DCE_RI_LSH 2
#define PBC_UART_CTRL_SET_DTE_DTR_LSH 8
// UART Control Clear Register
#define PBC_UART_CTRL_CLEAR_DCE_DCD_LSH 0
#define PBC_UART_CTRL_CLEAR_DCE_DSR_LSH 1
#define PBC_UART_CTRL_CLEAR_DCE_RI_LSH 2
#define PBC_UART_CTRL_CLEAR_DTE_DTR_LSH 8
// UART Status Register
#define PBC_UART_STATUS_DTE_DCD_LSH 0
#define PBC_UART_STATUS_DTE_DSR_LSH 1
#define PBC_UART_STATUS_DTE_RI_LSH 2
#define PBC_UART_STATUS_DCE_DTR_LSH 8
//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
// Version Register
#define PBC_VERSION_BOARD_VERSION_WID 8
// Board Control Register 1 Set/Clear Register
#define PBC_BCTRL1_ENET_RST_WID 1
#define PBC_BCTRL1_XUART_RST_WID 1
#define PBC_BCTRL1_FEC_RST_WID 1
#define PBC_BCTRL1_ENET_SLEEP_WID 1
#define PBC_BCTRL1_LED_1_WID 1
#define PBC_BCTRL1_LED_2_WID 1
#define PBC_BCTRL1_LCDON_WID 1
// Board Control Register 2 set/Clear Register
#define PBC_BCTRL2_VCC_EN_WID 1
#define PBC_BCTRL2_VPP_EN_WID 1
#define PBC_BCTRL2_ATA_FEC_EN_WID 1
#define PBC_BCTRL2_ATA_FEC_SEL_WID 1
#define PBC_BCTRL2_ATA_EN_WID 1
#define PBC_BCTRL2_IRDA_MOD_WID 1
#define PBC_BCTRL2_IRDA_EN_WID 1
#define PCB_BCTRL2_CCTL1_0_WID 1
#define PCB_BCTRL2_CCTL1_1_WID 1
// Board Control Register 3 Set/Clear Register
#define PBC_BCTRL3_HSH_EN_WID 1
#define PBC_BCTRL3_FSH_MODE_WID 1
#define PBC_BCTRL3_OTG_HS_EN_WID 1
#define PBC_BCTRL3_OTG_VBUS_EN_WID 1
#define PBC_BCTRL3_FSH_VBUS_EN_WID 1
#define PBC_BCTRL3_USB_OTG_ON_WID 1
#define PBC_BCTRL3_USB_FSH_ON_WID 1
// Board Control Register 4 Set/Clear Register
#define PBC_BCTRL4_REGEN_WID 1
#define PBC_BCTRL4_USER_OFF_WID 1
#define PBC_BCTRL4_VIB_EN_WID 1
#define PBC_BCTRL4_PWRGT1_EN_WID 1
#define PBC_BCTRL4_PWRGT2_EN_WID 1
#define PBC_BCTRL4_STDBY_PRI_WID 1
// Board Status Register 1
#define PBC_BSTAT1_PRI_INT_WID 1
#define PBC_BSTAT1_USB_BYP_WID 1
#define PBC_BSTAT1_ATA_IOCS16_WID 1
#define PBC_BSTAT1_ATA_CBLID_WID 1
#define PBC_BSTAT1_ATA_DASP_WID 1
#define PBC_BSTAT1_PWR_RDY_WID 1
#define PBC_BSTAT1_SD3_WP_WID 1
#define PBC_BSTAT1_SD2_WP_WID 1
#define PBC_BSTAT1_SD1_WP_WID 1
#define PBC_BSTAT1_SD3_DET_WID 1
#define PBC_BSTAT1_SD2_DET_WID 1
#define PBC_BSTAT1_SD1_DET_WID 1
#define PBC_BSTAT1_MS_DET_WID 1
// Interrupt Status Register
#define PBC_INT_LOW_BAT_WID 1
#define PBC_INT_OTG_FS_OVR_WID 1
#define PBC_INT_FSH_OVR_WID 1
#define PBC_INT_FEC_INT_WID 1
#define PBC_INT_ENET_INT_WID 1
#define PBC_INT_OTG_FS_INT_WID 1
#define PBC_INT_XUART_INT_WID 1
#define PBC_INT_CCTL1_2_WID 1
// Interrupt Current Status Register
#define PBC_INT_CUR_LOW_BAT_WID 1
#define PBC_INT_CUR_OTG_FS_OVR_WID 1
#define PBC_INT_CUR_FSH_OVR_WID 1
// Interrrupt Mask Register
#define PBC_INT_MASK_SD2_R_EN_WID 1
#define PBC_INT_MASK_LOW_BAT_WID 1
#define PBC_INT_MASK_OTG_FS_OVR_WID 1
#define PBC_INT_MASK_FSH_OVR_WID 1
#define PBC_INT_MASK_SD3_R_EN_WID 1
#define PBC_INT_MASK_MS_R_EN_WID 1
#define PBC_INT_MASK_SD1_R_EN_WID 1
#define PBC_INT_MASK_FEC_INT_WID 1
#define PBC_INT_MASK_ENET_INT_WID 1
#define PBC_INT_MASK_OTG_FS_INT_WID 1
#define PBC_INT_MASK_XUART_INT_WID 1
#define PBC_INT_MASK_CCTL1_2_WID 1
#define PBC_INT_MASK_SD2_EN_WID 1
#define PBC_INT_MASK_SD3_EN_WID 1
#define PBC_INT_MASK_MS_EN_WID 1
#define PBC_INT_MASK_SD1_EN_WID 1
// UART Control Set Register
#define PBC_UART_CTRL_SET_DCE_DCD_WID 1
#define PBC_UART_CTRL_SET_DCE_DSR_WID 1
#define PBC_UART_CTRL_SET_DCE_RI_WID 1
#define PBC_UART_CTRL_SET_DTE_DTR_WID 1
// UART Control Clear Register
#define PBC_UART_CTRL_CLEAR_DCE_DCD_WID 1
#define PBC_UART_CTRL_CLEAR_DCE_DSR_WID 1
#define PBC_UART_CTRL_CLEAR_DCE_RI_WID 1
#define PBC_UART_CTRL_CLEAR_DTE_DTR_WID 1
// UART Status Register
#define PBC_UART_STATUS_DTE_DCD_WID 0
#define PBC_UART_STATUS_DTE_DSR_WID 1
#define PBC_UART_STATUS_DTE_RI_WID 1
#define PBC_UART_STATUS_DCE_DTR_WID 1
//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// FUNCTION PROTOTYPES
//------------------------------------------------------------------------------
#ifdef __cplusplus
}
#endif
#endif // __PBC_H__
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