bsp_base_reg_cfg.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File:  bsp_base_reg_cfg.h
//
// This header file defines location for BSP on-board devices. It usually
// should contain only physical addresses. Virtual addresses should be obtain
// via OALPAtoVA function call. Base addresses for SoC are defined in similar
// file s3c2410x_base_reg_cfg.h.
//
//------------------------------------------------------------------------------
//
// NAMING CONVENTIONS
//
// BSP_BASE_REG_ is the standard prefix for BSP device base registers.
//
// Memory ranges are accessed using physical, uncached, or cached addresses,
// depending on the system state. The following abbreviations are used for
// each addressing type:
//
//      PA - physical address
//      CA - cached virtual address
//      UA - uncached virtual address
//
// The naming convention for base registers is:
//
//      xxx_BASE_REG_<ADDRTYPE>_<SUBSYSTEM>
//
//------------------------------------------------------------------------------
#ifndef __BSP_BASE_REG_CFG_H__
#define __BSP_BASE_REG_CFG_H__

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
// Define:  BSP_BASE_REG_PA_PBC_BASE
//
// Locates the PBC CPLD (PBC) module. WEIM CS4 is used
// to connect this device. Note that there must exist memory mapping in
// oemaddrtab_cfg.h for this memory area.
//
#define BSP_BASE_REG_PA_PBC_BASE            CSP_BASE_MEM_PA_CS4

//------------------------------------------------------------------------------
//
// Define:  BSP_BASE_REG_PA_CS8900A
//
// Locates CS8900A Ethernet chip. PBC is used
// to connect this device. Note that there must exist memory mapping in
// oemaddrtab_cfg.h for this memory area.
//
#define BSP_BASE_REG_PA_CS8900A_IOBASE      (BSP_BASE_REG_PA_PBC_BASE + PBC_CS8900_IOBASE_OFFSET + 0x300)
#define BSP_BASE_REG_PA_CS8900A_MEMBASE     (BSP_BASE_REG_PA_PBC_BASE + PBC_CS8900_MEMBASE_OFFSET)

//------------------------------------------------------------------------------
//
// Define:  BSP_BASE_REG_PA_SERIALKITL
//
// Specifies physical address of serial port used for serial KITL transport.
// We are initially using the on-chip UART1 for the serial KITL
// connection.  Note that there must exist memory mapping in
// oemaddrtab_cfg.h for this memory area.
//
#define BSP_BASE_REG_PA_SERIALKITL          CSP_BASE_REG_PA_UART1
	
#if __cplusplus
}
#endif

#endif // __BSP_BASE_REG_CFG_H__