bsp_clocks.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006,2007 Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: bsp_clocks.h
//
// This file contains macros for the different clocks available on MX27.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CLOCKS_H__
#define __BSP_CLOCKS_H__

//------------------------------------------------------------------------------
// Board clocks
//------------------------------------------------------------------------------
//
// OSC
//
// BSP_OSC_32K should be defined in environment if 32K oscillator is to be used.
// The frequency of 32K oscillator is default 32000 Hz, but can be 32768 from PMIC.
// This frequency is BSP_REF_32KHZ_FREQ defined as environment variable.
// The default value of 32000 comes from sources.cmn, and is default for the ADS.
// The EVB default BSP_REF_32KHZ_FREQ is 32768 and should be defined as environment var.
//
// BSP_OSC_26M and BSP_OSC_SEL are no longer used.  If BSP_OSC_32K is not defined 
// in environment, then the assumption will be that 26M crystal is used.
//

// DPLL = 2 * ref * (MFI + MFN / (MFD + 1)) / (PD + 1)
// BSP_OSC_32K: ref = 32.000K * 1024 = 32.768M (FPM_EN = 1, OSC26M_DIS = 1)
// !BSP_OSC_32K: ref = 26M / 1 = 26M (FPM_EN = 0, OSC26M_DIS = 0, OSC26M_DIV1P5 = 0)
//
// MPLL
//
#ifdef BSP_OSC_32K

#if (BSP_REF_32KHZ_FREQ == 32000)

#ifdef MX27TO2
#define BSP_MPLL_CLK_266        398998000
#define BSP_MPCTL0_PD           0
#define BSP_MPCTL0_MFI          6
#define BSP_MPCTL0_MFN          3 
#define BSP_MPCTL0_MFD          33
#else
#define BSP_MPLL_CLK_266        266008944
#define BSP_MPCTL0_PD           1
#define BSP_MPCTL0_MFI          8
#define BSP_MPCTL0_MFN          23
#define BSP_MPCTL0_MFD          194
#endif // MX27TO2

#else  // not 32000 Hz

#if (BSP_REF_32KHZ_FREQ == 32768)
#ifdef MX27TO2
#define BSP_MPLL_CLK_266        399000080
#define BSP_MPCTL0_PD           0
#define BSP_MPCTL0_MFI          5
#define BSP_MPCTL0_MFN          469
#define BSP_MPCTL0_MFD          495
#else  // MX27TO2
#define BSP_MPLL_CLK_266        266000054
#define BSP_MPCTL0_PD           3
#define BSP_MPCTL0_MFI          12
#define BSP_MPCTL0_MFN          239
#define BSP_MPCTL0_MFD          61
#endif // MX27TO2
#endif // 32768 Hz
#endif // 32000 Hz

#else // the following is for 26M crystal

#ifdef BSP_TVOUT
#ifdef MX27TO2 
#define BSP_MPLL_CLK_266        399600000
#define BSP_MPCTL0_PD           0
#define BSP_MPCTL0_MFI          7
#define BSP_MPCTL0_MFN          108
#define BSP_MPCTL0_MFD          269
#else // the following are for TO1
#define BSP_MPLL_CLK_266        266400000
#define BSP_MPCTL0_PD           1
#define BSP_MPCTL0_MFI          9
#define BSP_MPCTL0_MFN          234
#define BSP_MPCTL0_MFD          269
#endif // MX27TO2

#else // the following are for no TVOUT

#ifdef MX27TO2 
//------------------------------------------------------------------------------
// We should set MPLL as 400Mhz. then It will be 266Mhz by setting ARCSCR as 0
// 400 * 2 / 3  = 266Mhz
//------------------------------------------------------------------------------
#define BSP_MPLL_CLK_266        399000000
#define BSP_MPCTL0_PD           0
#define BSP_MPCTL0_MFI          7
#define BSP_MPCTL0_MFN          35
#define BSP_MPCTL0_MFD          51
#else // the following is for TO1
#define BSP_MPLL_CLK_266        266000000
#define BSP_MPCTL0_PD           1
#define BSP_MPCTL0_MFI          10
#define BSP_MPCTL0_MFN          6
#define BSP_MPCTL0_MFD          25
#endif // MX27TO2

#endif // BSP_TVOUT

#endif // BSP_OSC_32K

#define BSP_MPLL_CLK_FREQ       BSP_MPLL_CLK_266

//
// SPLL
//
#ifdef BSP_OSC_32K 

#if (BSP_REF_32KHZ_FREQ == 32000)
#define BSP_SPLL_CLK_240        240000000
#define BSP_SPCTL0_PD           1
#define BSP_SPCTL0_MFI          7
#define BSP_SPCTL0_MFN          83
#define BSP_SPCTL0_MFD          255

#else //not 32000 Hz

#if (BSP_REF_32KHZ_FREQ == 32768)
#define BSP_SPLL_CLK_240        240000000
#define BSP_SPCTL0_PD           1
#define BSP_SPCTL0_MFI          7
#define BSP_SPCTL0_MFN          9
#define BSP_SPCTL0_MFD          58

#endif //32768 Hz
#endif //32000 Hz

#else // the following is for 26M crystal

#ifdef BSP_TVOUT
#define BSP_SPLL_CLK_240        240000000
#define BSP_SPCTL0_PD           1
#define BSP_SPCTL0_MFI          8
#define BSP_SPCTL0_MFN          24
#define BSP_SPCTL0_MFD          26
#else // not TVOUT
#define BSP_SPLL_CLK_240        240000000
#define BSP_SPCTL0_PD           1
#define BSP_SPCTL0_MFI          9
#define BSP_SPCTL0_MFN          3
#define BSP_SPCTL0_MFD          12
#endif // BSP_TVOUT

#endif // BSP_OSC_32K

#define BSP_SPLL_CLK_FREQ       BSP_SPLL_CLK_240

//
// DIV & PRESC
//
#ifdef MX27TO2
#define BSP_CSCR_ARMSRC        1          // ARMINP = MPLL * 2 / 2 = 400M
#define BSP_CSCR_ARMDIV        0            // ARM_CLK = ARMINP / 1 = 400M
//   HCLK is kept same (133M) as in pre-TO2 (BSP_CSR_BCLKDIV)
#define BSP_CSCR_AHBDIV          1          // HCLK = MPLL*2 / (2*3) = 133M  
//   IPDIV isn't used in TO2, but kept here for data structure compatibility in args.c
#define BSP_CSCR_IPDIV          1         // IPG = HCLK / 2 = 66.5M
#define BSP_PCDR0_SSI1DIV       (14 << 1)   // SSI1 = SPLL / (14+2) = 15M
#define BSP_PCDR0_SSI2DIV       (14 << 1)   // SSI2 = SPLL / (14+2) = 15M
#define BSP_PCDR0_H264DIV       (0 << 1)    // H264 = MPLL / (0+2) = 133M
#define BSP_PCDR0_NFCDIV        9           // NFC = FCLK / 11 = 24.19M
#else
#define BSP_CSCR_PRESC          0           // FCLK = MPLL / 1 = 266M
#define BSP_CSCR_BCLKDIV        1           // HCLK = FCLK / 2 = 133M
#define BSP_CSCR_IPDIV          1           // IPG = HCLK / 2 = 66.5M
#define BSP_PCDR0_SSI1DIV       (16 << 1)   // SSI1 = SPLL / 16 = 15M
#define BSP_PCDR0_SSI2DIV       (16 << 1)   // SSI2 = SPLL / 16 = 15M
#define BSP_PCDR0_H264DIV       (2 << 1)    // H264 = MPLL / 2 = 133M
#define BSP_PCDR0_NFCDIV        13          // NFC = FCLK / 14 = 19M
#endif
#define BSP_CSCR_USB_DIV        3           // USB = SPLL / 4 = 60M
#define BSP_PCDR1_PERDIV1       7           // PERCLK1 = MPLL / 8 = 33.25M (UART, GPT, PWM)
#define BSP_PCDR1_PERDIV2       5           // PERCLK2 = MPLL / 6 = 44.33M (SDHC, CSPI)
#define BSP_PCDR1_PERDIV3       7           // PERCLK3 = MPLL / 8 = 33.25M (LCDC)
#define BSP_PCDR1_PERDIV4       4           // PERCLK4 = MPLL / 5 = 53.20M (CSI)
#define BSP_PCDR0_MSHCDIV       11          // MSHC (Serial, 20M) = SPLL / 12 = 20M

#endif // __BSP_CLOCKS_H__