oemaddrtab_cfg.inc

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;-------------------------------------------------------------------------------
;
; Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
; THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
; AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
;
;-------------------------------------------------------------------------------
;
; File:  oemaddrtab_cfg.inc
;
; This file is used to define g_oalAddressTable. This table is passed to
; KernelStart to estabilish physical to virtual memory mapping. This table
; is used also in IOMEM OAL module to map between physical and virtual
; memory addresses via OALPAtoVA/OALVAtoPA functions.
;
;-------------------------------------------------------------------------------

; Export Definition

    EXPORT  g_oalAddressTable[DATA]

;-------------------------------------------------------------------------------
;
; TABLE FORMAT
;       cached address, physical address, size
;-------------------------------------------------------------------------------

g_oalAddressTable

    DCD 0x88000000, CSP_BASE_MEM_PA_CSD0,       128     ; DDR RAM
    DCD 0x80000000, CSP_BASE_MEM_PA_CS0,        32      ; NOR Flash
    DCD 0x90000000, CSP_BASE_MEM_PA_CS2,        32      ; CS2
    DCD 0x92000000, CSP_BASE_MEM_PA_CS3,        32      ; CS3
    DCD 0x94000000, CSP_BASE_MEM_PA_CS4,        32      ; CPLD
    DCD 0x96000000, CSP_BASE_MEM_PA_CS5,        32      ; SRAM
    DCD 0x98000000, CSP_BASE_MEM_PA_PCMCIA_CF,  64      ; PCMCIA/CF
    DCD 0x9C000000, CSP_BASE_REG_PA_AIPI1,      1       ; Internal registers (AIPI1 + AIPI2 + AITC + ROM Patch)
    DCD 0x9C100000, CSP_BASE_REG_PA_CSI,        1       ; CSI + ATA
    DCD 0x9C200000, CSP_BASE_REG_PA_NANDFC,     1       ; EMI modules (NANDFC + ESDRAMC + WEIM + M3IF + PCMCIA)
    DCD 0x9C300000, CSP_BASE_MEM_PA_VRAM,       1       ; VRAM (45K)
    DCD 0x00000000, 0x00000000,                 0       ; Terminate table

;-------------------------------------------------------------------------------

    END