amd.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on
// your install media.
//
//-----------------------------------------------------------------------------
//
// Copyright (C) 2004,	Motorola Inc. All Rights Reserved
//
//-----------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//-----------------------------------------------------------------------------
//
// Header: amd.h
//
// Provides AMD flash specific definitions.
//
//------------------------------------------------------------------------------
#ifndef	__MX27_NORFLASH_AMD_H__
#define	__MX27_NORFLASH_AMD_H__

#ifdef __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// Defines
//
// Set to TRUE or FALSE to use unlock bypass enable if cannnot get info from
// CFI data.
// NOTE: default to enable since most newer AMD flash supports it.
#define DEFAULT_UNLOCK_BYPASS_ENABLE        FALSE

// Max page buffer datum
#define AMD_BUF_PROG_MAX_DATUM				32

// AMD's flash manufacturing code
#define AMD_MFG_ID                          0x0001
#define AMD_MFG_ID_x16                      AMD_MFG_ID
#define AMD_MFG_ID_x16_x2                   ((AMD_MFG_ID << 16) | AMD_MFG_ID)

// AMD cmd set
#define AMD_CMD_SET_ID					    0x0002

//
// Flash commands and status definitions.
//
#define CMD_RESET                           0xF0
#define CMD_PROGRAM_DATUM                   0xA0

#define CMD_ERASE                           0x80
#define CMD_SUSPEND_RESUME                  0xB0
#define FLASH_DATA_AA                       0xAA
#define FLASH_DATA_55                       0x55

// 16-bit mode
#define UNLOCK_ADDR1_x16                    0x0555
#define UNLOCK_ADDR2_x16                    0x02AA

// 8-bit mode
#define UNLOCK_ADDR1_x8                     0x0AAA
#define UNLOCK_ADDR2_x8                     0x0555

// reset the chip
// **************
#define CYCLE_1_ADDR_RESET                  0x000               // address is a don't care
#define CYCLE_1_DATA_RESET                  CMD_RESET

// common cycle 1-3 address and data
#define CYCLE_1_ADDR_UNLOCK_x16             UNLOCK_ADDR1_x16    // common address data cycle 1
#define CYCLE_1_DATA_UNLOCK                 FLASH_DATA_AA

#define CYCLE_2_ADDR_UNLOCK_x16             UNLOCK_ADDR2_x16    // common address data cycle 2
#define CYCLE_2_DATA_UNLOCK                 FLASH_DATA_55

#define CYCLE_3_ADDR_CMD_x16                UNLOCK_ADDR1_x16    // common address cycle 3

// autoselect
// **********
// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_AUTOSELECT             0x90
// the following are addresses for read device information
#define CYCLE_4_ADDR_MFG_ID                 0x00

#define CYCLE_4_ADDR_DEV_ID                 0x01
#define CYCLE_5_ADDR_DEV_ID                 0x0e
#define CYCLE_6_ADDR_DEV_ID                 0x0f

// secure silicon sector
// *********************
// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_ENTER_SECSI            0x88
#define CYCLE_3_DATA_EXIT_SECSI             0x90
#define CYCLE_4_ADDR_EXIT_SECSI             0x000               // address is a don't care
#define CYCLE_4_DATA_EXIT_SECSI             0x00

// program datum
// *************
// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_PROGRAM                CMD_PROGRAM_DATUM
//#define_CYCLE_4_ADDR_PROGRAM is the array address
//#define_CYCLE_4_DATA_PROGRAM is the datum

// write buffer
// ************
// write data to buffer
// uses common cycle 1-2 address and data
//#define_CYCLE_3_ADDR_WR_BUFF is the sector address
#define CYCLE_3_DATA_WR_BUFR                0x25
//#define_CYCLE_4_ADDR_WR_BUFF is the sector address
//#define CYCLE_4_DATA_WR_BUFR is the word (16-bit datum) count
//#define_CYCLE_5_ADDR_WR_BUFF is the array address (must be within the given sector)
//#define CYCLE_5_DATA_WR_BUFR is the word (16-bit datum) value
//#define_CYCLE_6_ADDR_WR_BUFF is the write buffer address (must be within the same page as array address in cycle 5)
//#define CYCLE_6_DATA_WR_BUFR is the word (16-bit datum) value
//#define_CYCLE_6+n_ADDR_WR_BUFF is the write buffer address (must be within the same page as array address in cycle 5)
//#define CYCLE_6+n_DATA_WR_BUFR is the word (16-bit datum) value

// program buffer
// **************
//#define_CYCLE_1_ADDR_WR_BUFF_PROGRAM is the sector address
#define CYCLE_1_DATA_WR_BUFR_PROGRAM        0x29

// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_RESET_WR_BUFR          CMD_RESET

// bypass program
// **************
// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_UNLOCK_BYPASS          0x20

#define CYCLE_1_ADDR_PROGRAM_BYPASS         0x00                // address is a don't care
#define CYCLE_1_DATA_PROGRAM_BYPASS         CMD_PROGRAM_DATUM
//#define_CYCLE_2_ADDR_PROGRAM is the array address
//#define_CYCLE_2_DATA_PROGRAM is the datum

#define CYCLE_1_ADDR_RESET_BYPASS           0x00                // address is a don't care
#define CYCLE_1_DATA_RESET_BYPASS           0x90
#define CYCLE_2_ADDR_RESET_BYPASS           0x00                // address is a don't care
#define CYCLE_2_DATA_RESET_BYPASS           0x00

// erase
// *****
// uses common cycle 1-2 address and data and cycle 3 address
#define CYCLE_3_DATA_ERASE                  CMD_ERASE
#define CYCLE_4_ADDR_ERASE                  UNLOCK_ADDR1_x16    
#define CYCLE_4_DATA_ERASE                  FLASH_DATA_AA
#define CYCLE_5_ADDR_ERASE                  UNLOCK_ADDR2_x16    
#define CYCLE_5_DATA_ERASE                  FLASH_DATA_55

// erase chip
// **********
#define CYCLE_6_ADDR_CHIP_ERASE             UNLOCK_ADDR1_x16    
#define CYCLE_6_DATA_CHIP_ERASE             0x10

// erase sector
// ************
//#define_CYCLE_6_ADDR_SECTOR_ERASE is the sector address
#define CYCLE_6_DATA_SECTOR_ERASE           0x30

// suspend
// *******
#define CYCLE_1_ADDR_SUSPEND                CMD_SUSPEND_RESUME
#define CYCLE_1_DATA_SUSPEND                0xB0

// resume
// *******
#define CYCLE_1_ADDR_RESUME                 CMD_SUSPEND_RESUME
#define CYCLE_1_DATA_RESUME                 0x30

// DYB 
// *******
#define CYCLE_3_DATA_DYB_WRITE              0x48
#define CYCLE_4_DATA_DYB_WRITE              0x01
#define CYCLE_3_DATA_DYB_ERASE              0x48
#define CYCLE_4_DATA_DYB_ERASE              0x00
#define CYCLE_3_DATA_DYB_STATUS             0x58

// DQ5 status
#define AMD_FLASH_DQ5_X16                  (1 << 5)
#define AMD_FLASH_DQ5_X16_H                UPPER(AMD_FLASH_DQ5_X16)

// DQ6 status
#define AMD_FLASH_DQ6_X16                  (1 << 6)
#define AMD_FLASH_DQ6_X16_H                UPPER(AMD_FLASH_DQ6_X16)

// DQ7 status
#define AMD_FLASH_DQ7_X16                  (1 << 7)
#define AMD_FLASH_DQ7_X16_H                UPPER(AMD_FLASH_DQ7_X16)

// DQ1 status
#define AMD_FLASH_DQ1_X16                  (1 << 1)
#define AMD_FLASH_DQ1_X16_H                UPPER(AMD_FLASH_DQ1_X16)

// Max number of banks in flash
#define AMD_MAX_NUM_BANKS                  32

//------------------------------------------------------------------------------
// Types
#pragma pack(1)
// AMD Primary Vendor-Specific Extended Query 
// support v1.4 
typedef struct _AMD_PET_QUERY {
    CHAR ID[3];
    CHAR VersionMajor;
    CHAR VersionMinor;
    UCHAR AddrUnlockSiTech;
    UCHAR EraseSuspendSupport;
    UCHAR SectorProtectGroupSize;
    UCHAR SectorTempUnprotectSupport;
    UCHAR SectorProtectScheme;
    UCHAR SimulOperationSupport;
    UCHAR BurstModeSupport;
    UCHAR PageModeSupport;
    UCHAR ACCVmin;
    UCHAR ACCVmax;
    UCHAR BootSectorSupport;
    UCHAR ProgramSuspendSupport;
    UCHAR UnlockBypassSupport;
    UCHAR SecSiSize;
    UCHAR EmbeddedHwResetTOMax_ns;
    UCHAR NonEmbeddedHwResetTOMax_ns;
    UCHAR EraseSuspendTOMax_us;
    UCHAR ProgramSuspendTOMax_us;
    UCHAR NumBanks;
    UCHAR SectorsInBank[AMD_MAX_NUM_BANKS];
} AMD_PET_QUERY_INFO, *PAMD_PET_QUERY_INFO;
#pragma pack()

//------------------------------------------------------------------------------
// Functions
//
// Supported specific low level flash drivers
// ******************************************
// AMD flash driver (x16 devices)
void AMDx16_RelocateBegin(void);
BOOL AMDx16_IsFlashSupported(NOR_FLASH_DESC *pFlashDesc);
BOOL AMDx16_Program(NOR_FLASH_DESC *pFlashDesc, ULONG ulStartAddress, UCHAR *pData, ULONG ulSize, BOOL bIgnore0to1);
BOOL AMDx16_EraseSector(NOR_FLASH_DESC *pFlashDesc, ULONG ulSectorAddress);
BOOL AMDx16_EraseChip(NOR_FLASH_DESC *pFlashDesc);
void AMDx16_RelocateEnd(void);
void AMDx16_Reset(NOR_FLASH_DESC *pFlashDesc);
BOOL AMDx16_LockSector(NOR_FLASH_DESC *pFlashDesc, ULONG ulSectorAddress);
BOOL AMDx16_UnlockSector(NOR_FLASH_DESC *pFlashDesc, ULONG ulSectorAddress);
BOOL AMDx16_IsSectorLocked(NOR_FLASH_DESC *pFlashDesc, ULONG ulSectorAddress);

#ifdef __cplusplus
    }
#endif

#endif // __MX27_NORFLASH_AMD_H__