📄 socket.h
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/*
*
* Copyright (C) 2003-2004, MOTOROLA, INC. All Rights Reserved
* THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
* BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
* MOTOROLA, INC.
*
* Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
* THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
* AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
*
* File: DRIVERS\PCCARD\socket.h
* Purpose: PCMCIA Controller Codes
*
* Notes:
*
*/
#ifndef SOCKET_H
#define SOCKET_H
#include <nkintr.h>
#include "csp.h"
/*********************************************************************
MACRO DEFINITIONS
*********************************************************************/
// BVD1_SPKRIN: Batt Voltage Detect1 in Mem mode, SPKR-In in IO mode
// #define PCMCIA_PIPR_BVD1_STSCHG (1 << 5)
// CD: CardDetect1/2
#define PCMCIA_PIPR_CARDDETECT2 (1 << 4)
#define PCMCIA_PIPR_CARDDETECT1 (1 << 3)
#define PCMCIA_PIPR_CARDDETECT (3 << 3)
// WP: WriteProtect
#define PCMCIA_PIPR_WRITEPROTECT (1 << 2)
// VS: VoltageSense
#define PCMCIA_PIPR_VOLTSENSE_33 (1 << 0)
#define PCMCIA_PIPR_VOLTSENSE_50 (2 << 0)
// PSCR : PCMCIA Status Change Register
// POWC: PowerON
#define PCMCIA_PSCR_POWERON_CH (1 << 11)
// RDYF: Ready Rising Edge
#define PCMCIA_PSCR_RDY_RISINGINTR_CH (1 << 10)
// RDYR: Ready Falling Edge
#define PCMCIA_PSCR_RDY_FALLINGINTR_CH (1 << 9)
// RDYH: Ready High
#define PCMCIA_PSCR_RDY_HIGHINTR_CH (1 << 8)
// RDYL: Ready Low
#define PCMCIA_PSCR_RDY_LOWINTR_CH (1 << 7)
// BVDC2: Batt Voltage Detect 2 / Speaker-In Changed
#define PCMCIA_PSCR_BVD2_SPKRIN_CH (1 << 6)
// BVDC2: Batt Voltage Detect 1 / STSCHG Changed
#define PCMCIA_PSCR_BVD1_STSCHG_CH (1 << 5)
// CDC1 CDC2: Card Detect1/2 Changed
#define PCMCIA_PSCR_CARDDETECT2_CH (1 << 4)
#define PCMCIA_PSCR_CARDDETECT1_CH (1 << 3)
#define PCMCIA_PSCR_CARDDETECT_CH (3 << 3)
// WPC: Write Protect Changed
#define PCMCIA_PSCR_WRITEPROTECT_CH (1 << 2)
// VSC1 VSC2: Voltage Sense1/2 Changed
#define PCMCIA_PSCR_VOLTSENSE_CH (3 << 0)
// PER : PCMCIA Enable Register
// ERRINTEN: Err Intr Enable
#define PCMCIA_PER_ERRORINTR_EN (1 << 12)
// POWERONEN: PowerON Intr Enable
#define PCMCIA_PER_POWERON_EN (1 << 11)
// RDYRE: Ready Rising Edge Intr Enable
#define PCMCIA_PER_RDY_RISINGINTR_EN (1 << 10)
// RDYFE: Ready Falling Edge Intr Enable
#define PCMCIA_PER_RDY_FALLINGINTR_EN (1 << 9)
// RDYHE: Ready High Intr Enable
#define PCMCIA_PER_RDY_HIGHINTR_EN (1 << 8)
// RDYLE: Ready Low Intr Enable
#define PCMCIA_PER_RDY_LOWINTR_EN (1 << 7)
// BVDE2: Batt Volt 2 / Speaker-In Intr Enable
#define PCMCIA_PER_BVD2_SPKRIN_EN (1 << 6)
// BVDE1: Batt Volt 1 / STSCHHG Intr Enable
#define PCMCIA_PER_BVD1_STSCHG_EN (1 << 5)
// CDE1 CDE2: Card Detect 1/2 Intr Enable
#define PCMCIA_PER_CARDDETECT_EN (3 << 3)
// WPE: Write Protect Intr Enable
#define PCMCIA_PER_WRITEPROTECT_EN (1 << 2)
// VSE1 VSE2: Voltage Sense 1/2 Intr Enable
#define PCMCIA_PER_VOLTSENSE_EN (3 << 0)
// POR : PCMCIA Option Register [0-6]
// PV: Valid
#define PCMCIA_POR_PVALID (1 << 29)
// WPEN: Write Protect Input Enable
#define PCMCIA_POR_WPEN (1 << 28)
// WP: Write Protect Enable
#define PCMCIA_POR_WRITEPROTECT (1 << 27)
// PRS: Region Select
#define PCMCIA_POR_REGIONSELECT_BS 25
#define PCMCIA_POR_REGIONSELECT (3 << PCMCIA_POR_REGIONSELECT_BS)
// PPS: Port Size
#define PCMCIA_POR_PORTSIZE_BS 24
#define PCMCIA_POR_PORTSIZE (1 << PCMCIA_POR_PORTSIZE_BS)
// PSL: PCMCIA Strobe Length
#define PCMCIA_POR_PSL_BS 17
#define PCMCIA_POR_PSL (127 << PCMCIA_POR_PSL_BS)
// PSH: PCMCIA Strobe Hold Time
#define PCMCIA_POR_PSST_BS 11
#define PCMCIA_POR_PSST (63 << PCMCIA_POR_PSST_BS)
// PSS: PCMCIA Strobe Setup Time
#define PCMCIA_POR_PSHT_BS 5
#define PCMCIA_POR_PSHT (63 << PCMCIA_POR_PSHT_BS)
// BSIZE: Bank Size
#define PCMCIA_POR_BSIZE_BS 0
#if (MX21_TO_VER >= 20)
#define PCMCIA_POR_BSIZE (15 << PCMCIA_POR_BSIZE_BS)
#else
#define PCMCIA_POR_BSIZE (31 << PCMCIA_POR_BSIZE_BS)
#endif
// LPMEN: Low Power Mode Enable
#define PCMCIA_PGCR_LOWPWRMODE (1 << 3)
// SPKREN: Speaker Enable
#define PCMCIA_PGCR_SPKREN (1 << 2)
// POE: Controller Output Enable
#define PCMCIA_PGCR_OUTPUTEN (1 << 1)
// RESET: Card Reset
#define PCMCIA_PGCR_RESET (1 << 0)
// PGSR: PCMCIA General Status Register
// NWINE: No Window Error
#define PCMCIA_PGSR_NOWINDOW_ERR (1 << 4)
// LPE: Low Power Error
#define PCMCIA_PGSR_LOWPWR_ERR (1 << 3)
// SE: Size Error
#define PCMCIA_PGSR_SIZE_ERR (1 << 2)
// CDE: Card Detect Error
#define PCMCIA_PGSR_CARDDETECT_ERR (1 << 1)
// WPE: Write Protect Error
#define PCMCIA_PGSR_WRITEPROTECT_ERR (1 << 0)
// POR Region Select
#define PCMCIA_REGIONSELECT_COMMON 0x0
#define PCMCIA_REGIONSELECT_TRUEIDE 0x1
#define PCMCIA_REGIONSELECT_ATTRIBUTE 0x2
#define PCMCIA_REGIONSELECT_IO 0x3
// POR Port Size
#define PCMCIA_PORTSIZE_16BIT 0x0
#define PCMCIA_PORTSIZE_8BIT 0x1
/*
* In TO1 max bank size: 64MB, TO2: 2KB, TO3: 32KB
* POR BankSize, Note: BankSize in Spec is not in sequence
* Left(L): Actual BankSize value Right(R): Register value
*/
#define PCMCIA_BANKSIZE_0 0 // L:2^0 = 1
#define PCMCIA_BANKSIZE_1 1 // L:2^1 = 2
#define PCMCIA_BANKSIZE_2 3 // L:2^2 = 4
#define PCMCIA_BANKSIZE_3 2 // L:2^3 = 8
#define PCMCIA_BANKSIZE_4 6 // L:2^4 = 16
#define PCMCIA_BANKSIZE_5 7 // L:2^5 = 32
#define PCMCIA_BANKSIZE_6 5 // L:2^6 = 64
#define PCMCIA_BANKSIZE_7 4 // L:2^7 = 128
#define PCMCIA_BANKSIZE_8 12 // L:2^8 = 256
#define PCMCIA_BANKSIZE_9 13 // L:2^9 = 512
#define PCMCIA_BANKSIZE_10 15 // L:2^10= 1 KB
#define PCMCIA_BANKSIZE_11 14 // L:2^11= 2 KB
#define PCMCIA_BANKSIZE_12 10 // L:2^12= 4 KB
#define PCMCIA_BANKSIZE_13 11 // L:2^13= 8 KB
#define PCMCIA_BANKSIZE_14 9 // L:2^14= 16 KB
#define PCMCIA_BANKSIZE_15 8 // L:2^15= 32 KB
#define PCMCIA_BANKSIZE_16 24 // L:2^16= 64 KB
#define PCMCIA_BANKSIZE_17 25 // L:2^17= 128 KB
#define PCMCIA_BANKSIZE_18 27 // L:2^18= 256 KB
#define PCMCIA_BANKSIZE_19 26 // L:2^19= 512 KB
#define PCMCIA_BANKSIZE_20 30 // L:2^20= 1 MB
#define PCMCIA_BANKSIZE_21 31 // L:2^21= 2 MB
#define PCMCIA_BANKSIZE_22 29 // L:2^22= 4 MB
#define PCMCIA_BANKSIZE_23 28 // L:2^23= 8 MB
#define PCMCIA_BANKSIZE_24 20 // L:2^24= 16 MB
#define PCMCIA_BANKSIZE_25 21 // L:2^25= 32 MB
#define PCMCIA_BANKSIZE_26 23 // L:2^26= 64 MB
#if (MX21_TO_VER >= 30)
#define PCMCIA_ADDRESS_OFFSET_MASK (0x00007FF0) // [4:14] bits access
#define PCMCIA_BSIZE_BIT_OFFSET (4) // 4bit Offset
#define PCMCIA_BANKSIZE_MAX (32 * 1024) // Max Bank Size = 32 KB
#elif (MX21_TO_VER >= 20)
#define PCMCIA_ADDRESS_OFFSET_MASK (0x000007FF) // [0:11] bits access
#define PCMCIA_BSIZE_BIT_OFFSET (0) // No offset
#define PCMCIA_BANKSIZE_MAX (2 * 1024) // Max Bank Size = 2 KB
#elif (MX27_TO_VER >= 0)
// MX27 PCMCIA Controller supports [0:25] bits access
// But since only 64MB memory map is available, we assume currently 1MB windows
// Thereby only [0:20] bits access are used
#define PCMCIA_ADDRESS_OFFSET_MASK (0x00FFFFFF) // [0:20] bits access
#define PCMCIA_BSIZE_BIT_OFFSET (0) // No offset
#define PCMCIA_BANKSIZE_MAX (64 * 1024 * 1024) // Max Bank Size = 64 MB
#else
#define PCMCIA_ADDRESS_OFFSET_MASK (0x03FFFFFF) // [0:25] bits access
#define PCMCIA_BSIZE_BIT_OFFSET (0) // No offset
#define PCMCIA_BANKSIZE_MAX (64 * 1024 * 1024) // Max Bank Size = 64 MB
#endif
#define PCMCIA_BANKSIZE_MIN (1 << PCMCIA_BSIZE_BIT_OFFSET) // Min Bank Size = 1 byte
// 7 Windows in TO1.1 & earlier, 5 windows in TO2 & later
// We'll just use 4 windows regardless of silicon revision.
#if (MX21_TO_VER >= 20)
#define PCMCIA_NUM_HW_WINDOWS 5
#else
#define PCMCIA_NUM_HW_WINDOWS 7
#endif
#define PCMCIA_NUM_WINDOWS 4
#define PCMCIA_NUM_IOWIN 2
#define PCMCIA_NUM_MEMWIN (PCMCIA_NUM_WINDOWS - PCMCIA_NUM_IOWIN)
// The last 2 windows are configured as IO Windows
// For total windows = 4: window 0-1 = Memory (common / attribute), window 2-3 = IO windows
#define SOCKET_FIRST_MEMORY_WINDOW 0
#define SOCKET_FIRST_IO_WINDOW PCMCIA_NUM_MEMWIN
// Reset/Clear PCMCIA Socket
#define PCMCIA_RESET_SOCKET(val) ((val == 1)? g_vPcmciaReg->PGCR |= PCMCIA_PGCR_RESET : g_vPcmciaReg->PGCR &= ~PCMCIA_PGCR_RESET)
#define IS_CARD_INSERTED(status) ((status&PCMCIA_PIPR_CARDDETECT)==0)
#define IS_BVD1_SET(status) ((status & CSP_BITFVAL(PCMCIA_PIPR_BVD1, PCMCIA_PIPR_BVD1_STSCHG))!=0)
#define IS_BVD2_SET(status) ((status & CSP_BITFVAL(PCMCIA_PIPR_BVD2, PCMCIA_PIPR_BVD2_SPKRIN))!=0)
#define IS_WP_SET(status) ((status & PCMCIA_PIPR_WRITEPROTECT)!=0)
#define IS_READY_IREQ_SET(status) ((status & CSP_BITFVAL(PCMCIA_PIPR_RDY, PCMCIA_PIPR_RDY_RDY))==0) // only care about the IO mode
#define IS_POWERON_SET(status) ((status & CSP_BITFVAL(PCMCIA_PIPR_POWERON, PCMCIA_PIPR_POWERON_ON))!=0)
#define IS_CARDDETEC_CHANGE(status) ((status & PCMCIA_PSCR_CARDDETECT_CH)!=0)
#define IS_BVD1_CHANGE(status) ((status & PCMCIA_PSCR_BVD1_STSCHG_CH)!=0)
#define IS_BVD2_CHANGE(status) ((status & PCMCIA_PSCR_BVD2_SPKRIN_CH)!=0)
#define IS_WP_CHANGE(status) ((status & PCMCIA_PSCR_WRITEPROTECT_CH)!=0)
#define IS_READY_IREQ_CHANGE(status) ((status & PCMCIA_PSCR_RDY_LOWINTR_CH)!=0)
#define IS_POWERON_CHANGE(status) ((status & PCMCIA_PSCR_POWERON_CH)!=0)
#define CLEAR_CARD_ERROR_STATUS(status) (g_vPcmciaReg->PGSR |= status)
#define CLEAR_CARD_STATUS_CHANGE(status) (g_vPcmciaReg->PSCR |= status)
#define GET_CARD_STATUS() (g_vPcmciaReg->PIPR)
#define GET_CARD_STATUS_CHANGE() (g_vPcmciaReg->PSCR)
#define GET_CARD_ERROR_STATUS() (g_vPcmciaReg->PGSR)
// Default value for wait states
#define PCMCIA_POR_PSL_BS_DEFAULT 20
#define PCMCIA_POR_PSST_BS_DEFAULT 10
#define PCMCIA_POR_PSHT_BS_DEFAULT 10
/*********************************************************************
ENUMERATIONS AND STRUCTURES
*********************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*********************************************************************
FUNCTION PROTOTYPES
*********************************************************************/
void PcPrintPcmciaReg(void);
/*********************************************************************
EXTERN DECLARATIONS
*********************************************************************/
// pcmcia register
extern PCSP_PCCARD_REGS g_vPcmciaReg;
#ifdef __cplusplus
}
#endif
/*********************************************************************
CLASS DEFINITIONS
*********************************************************************/
#endif /* SOCKET_H */
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