intr.c

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File: intr.c
//
//  This file implements the major part of interrupt support for the 
//  MX27 SoC.
//
//------------------------------------------------------------------------------
#include <windows.h>
#include <ceddk.h>
#include <nkintr.h>
#include <cmnintrin.h>
#include <oal.h>
#include "csp.h"
#include <intr.h>



//------------------------------------------------------------------------------
// External Functions


//------------------------------------------------------------------------------
// External Variables

//------------------------------------------------------------------------------
// Defines

//------------------------------------------------------------------------------
// Types


//------------------------------------------------------------------------------
// Global Variables
PCSP_AITC_REGS g_pAITC;
PCSP_GPIO_REGS g_pGPIO;
BOOL g_bBSPIrq = FALSE;

//  Function pointer to profiling timer ISR routine.
//
PFN_PROFILER_ISR g_pProfilerISR = NULL;

UINT32 g_IRQ_RTC = IRQ_RTIC;

//------------------------------------------------------------------------------
//
//  Function:  OALIntrInit
//
//  This function initialize interrupt mapping, hardware and call platform
//  specific initialization.
//
BOOL OALIntrInit()
{
    BOOL rc = FALSE;
    GPIO_PORT port;

    OALMSG( OAL_FUNC&&OAL_INTR, (L"+OALInterruptInit\r\n") );

    // Initialize interrupt mapping
    OALIntrMapInit();

    // Get uncached virtual addresses for AITC
    g_pAITC = (PCSP_AITC_REGS) OALPAtoUA(CSP_BASE_REG_PA_AITC);
    if (g_pAITC == NULL)
    {
        OALMSG(OAL_ERROR, (L"OALIntrInit:  AITC null pointer!\r\n"));
        goto cleanUp;
    }

    // Get uncached virtual addresses for GPIO modules
    g_pGPIO = (PCSP_GPIO_REGS)OALPAtoUA(CSP_BASE_REG_PA_GPIO);
    if (g_pGPIO == NULL)
    {
        OALMSG(OAL_ERROR, (L"OALIntrInit:  GPIO null pointer!\r\n"));
        goto cleanUp;
    }

    // Enable normal interrupt to raise ARM core priority in bus request
    OUTREG32(&g_pAITC->INTCNTL, CSP_BITFMASK(AITC_INTCNTL_NIAD));
     
    // Mask and clear all GPIO IRQs,Unmask GPIO port level interrupt
    for(port = GPIO_PORT_A; port < GPIO_PORT_MAX; port++)
    {
        g_pGPIO->PORT[port].IMR = 0;
        g_pGPIO->PORT[port].ISR = 0xFFFFFFFF;
        g_pGPIO->PMASK |= (1 << port);
    }    
 
#ifdef OAL_BSP_CALLBACKS
    // Give BSP chance to initialize subordinate controller
    rc = BSPIntrInit();
#else
    rc = TRUE;
#endif

cleanUp:
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-OALInterruptInit(rc = %d)\r\n", rc));
    return rc;
}



//------------------------------------------------------------------------------
//
//  Function:  OALIntrRequestIrqs
//
//  This function returns IRQs for CPU/SoC devices based on their
//  physical address.
//
BOOL OALIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+OALIntrRequestIrqs(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n",
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    )); 

    if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto cleanUp;

   switch (pDevLoc->IfcType) 
    {
    case Internal:

        switch (pDevLoc->LogicalLoc)
        {
        case CSP_BASE_REG_PA_I2C2:
            pIrqs[0] = IRQ_I2C2;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_GPT6:
            pIrqs[0] = IRQ_GPT6;
            *pCount = 1;
            rc = TRUE;
            break;	

        case CSP_BASE_REG_PA_GPT5:
            pIrqs[0] = IRQ_GPT5;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_GPT4:
            pIrqs[0] = IRQ_GPT4;
            *pCount = 1;
            rc = TRUE;
            break;
			
        case CSP_BASE_REG_PA_RTIC:
            pIrqs[0] = IRQ_RTIC;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_CSPI3:
            pIrqs[0] = IRQ_CSPI3;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_MSHC:
            pIrqs[0] = IRQ_MSHC;
            *pCount = 1;
            rc = TRUE;
            break;
			
        case CSP_BASE_REG_PA_GPIO:
            pIrqs[0] = IRQ_GPIO;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_SDHC3:
            pIrqs[0] = IRQ_SDHC3;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_SDHC2:
            pIrqs[0] = IRQ_SDHC2;
            *pCount = 1;
            rc = TRUE;
            break;
			
        case CSP_BASE_REG_PA_SDHC1:
            pIrqs[0] = IRQ_SDHC1;
            *pCount = 1;
            rc = TRUE;
            break;
			
        case CSP_BASE_REG_PA_I2C1:
            pIrqs[0] = IRQ_I2C1;
            *pCount = 1;
            rc = TRUE;
            break;
            
        case CSP_BASE_REG_PA_SSI2:
            pIrqs[0] = IRQ_SSI2;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_SSI1:
            pIrqs[0] = IRQ_SSI1;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_CSPI2:
            pIrqs[0] = IRQ_CSPI2;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_CSPI1:
            pIrqs[0] = IRQ_CSPI1;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_UART4:
            pIrqs[0] = IRQ_UART4;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_UART3:
            pIrqs[0] = IRQ_UART3;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_UART2:
            pIrqs[0] = IRQ_UART2;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_UART1:
            pIrqs[0] = IRQ_UART1;
            *pCount = 1;
            rc = TRUE;
            break;
			

        case CSP_BASE_REG_PA_KPP:
            pIrqs[0] = IRQ_KPP;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_RTC:
            pIrqs[0] = IRQ_RTC;
            *pCount = 1;
            rc = TRUE;
            break;
			
        case CSP_BASE_REG_PA_PWM:
            pIrqs[0] = IRQ_PWM;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_GPT3:
            pIrqs[0] = IRQ_GPT3;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_GPT2:
            pIrqs[0] = IRQ_GPT2;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_GPT1:
            pIrqs[0] = IRQ_GPT1;
            *pCount = 1;
            rc = TRUE;
            break;				

        case CSP_BASE_REG_PA_WDOG:
            pIrqs[0] = IRQ_WDOG;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_PCMCIA:
            pIrqs[0] = IRQ_PCMCIA;  // Slammed SIM IRQ
            *pCount = 1;
            rc = TRUE;
            break;
            
        case CSP_BASE_REG_PA_NANDFC:
            pIrqs[0] = IRQ_NFC;
            *pCount = 1;
            rc = TRUE;
            break;
            
        case CSP_BASE_REG_PA_ATA:
            pIrqs[0] = IRQ_ATA;
            *pCount = 1;
            rc = TRUE;
            break;
            
        case CSP_BASE_REG_PA_CSI:
            pIrqs[0] = IRQ_CSI;
            *pCount = 1;
            rc = TRUE;
            break;
            
        case CSP_BASE_REG_PA_UART6:
            pIrqs[0] = IRQ_UART6;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_UART5:
            pIrqs[0] = IRQ_UART5;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_FEC:
            pIrqs[0] = IRQ_FEC;
            *pCount = 1;
            rc = TRUE;
            break;

        case CSP_BASE_REG_PA_EMMA:
           // Check if output array can hold all IRQs
            if (*pCount >= 2)
            {
                pIrqs[0] = IRQ_EMMAPRP;
                pIrqs[1] = IRQ_EMMAPP;
                *pCount = 2;
                rc = TRUE;
            }
            break;