mx27_sysctrl.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

#define SYSCTRL_FMCR_NF_FMS_WID                 1
#define SYSCTRL_FMCR_IOIS16_CTL_WID             1
#define SYSCTRL_FMCR_PC_BVD2_CTL_WID            1
#define SYSCTRL_FMCR_PC_BVD1_CTL_WID            1
#define SYSCTRL_FMCR_PC_VS2_CTL_WID             1
#define SYSCTRL_FMCR_PC_VS1_CTL_WID             1
#define SYSCTRL_FMCR_PC_READY_CTL_WID           1
#define SYSCTRL_FMCR_PC_WAIT_B_CTL_WID          1
#define SYSCTRL_FMCR_KP_ROW6_CTL_WID            1
#define SYSCTRL_FMCR_KP_ROW7_CTL_WID            1
#define SYSCTRL_FMCR_KP_COL6_CTL_WID            1
#define SYSCTRL_FMCR_UART4_RTS_CTL_WID          1
#define SYSCTRL_FMCR_UART4_RXD_CTL_WID          1

// GPCR
#define SYSCTRL_GPCR_CLK_DDR_MODE_WID           1
#define SYSCTRL_GPCR_DDR_MODE_WID               1
#define SYSCTRL_GPCR_CLOCK_GATING_EN_WID        1
#define SYSCTRL_GPCR_DMA_BURST_OVERRIDE_WID     1
#define SYSCTRL_GPCR_PP_BURST_OVERRIDE_WID      1
#define SYSCTRL_GPCR_USB_BURST_OVERRIDE_WID     1
#define SYSCTRL_GPCR_ETM9_PAD_EN_WID            1
#define SYSCTRL_GPCR_BOOT_WID                   4

// WBCR
#define SYSCTRL_WBCR_CRM_WBM_WID                3
#define SYSCTRL_WBCR_CRM_WBFA_WID               1
#define SYSCTRL_WBCR_CRM_SPA_BIT01_WID          2
#define SYSCTRL_WBCR_CRM_SPA_BIT23_WID          2
#define SYSCTRL_WBCR_CRM_WBM_EMI_WID            3
#define SYSCTRL_WBCR_CRM_WBFA_EMI_WID           1
#define SYSCTRL_WBCR_CRM_SPA_EMI_BIT01_WID      2
#define SYSCTRL_WBCR_CRM_SPA_EMI_BIT23_WID      2

//DSCR1
#define SYSCTRL_DSCR1_DS_SLOW11_DVS_PMIC_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW10_SDHC1_CSPI3_WID 	2
#define SYSCTRL_DSCR1_DS_SLOW9_JTAG_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW8_PWM_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW7_CSPI1_WID 	2
#define SYSCTRL_DSCR1_DS_SLOW6_SSI1_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW5_GPT1_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW4_USBH1_WID 	2
#define SYSCTRL_DSCR1_DS_SLOW3_CSI_WID 		2
#define SYSCTRL_DSCR1_DS_SLOW2_SDHC2_MSHC_WID 	2
#define SYSCTRL_DSCR1_DS_SLOW1_LCDC_WID 		2

//PSCR
#define SYSCTRL_PSCR_SD2_D0_PUENCR_WID	2
#define SYSCTRL_PSCR_SD2_D1_PUENCR_WID	2
#define SYSCTRL_PSCR_SD2_D2_PUENCR_WID	2
#define SYSCTRL_PSCR_SD2_D3_PUENCR_WID	2
#define SYSCTRL_PSCR_SD2_CMD_PUENCR_WID	2
#define SYSCTRL_PSCR_SD2_CLK_PUENCR_WID	2
#define SYSCTRL_PSCR_SD1_D3_PUENCR_WID	2
#define SYSCTRL_PSCR_ATA_DAT3_PUENCR_WID	2

// PCSR
#define SYSCTRL_PCSR_S0_AMPR_SEL_WID            1
#define SYSCTRL_PCSR_S1_AMPR_SEL_WID            1
#define SYSCTRL_PCSR_S2_AMPR_SEL_WID            1
#define SYSCTRL_PCSR_S3_AMPR_SEL_WID            1

// PMCR
#define SYSCTRL_PMCR_DPTEN_WID                  1
#define SYSCTRL_PMCR_DIE_WID                    1
#define SYSCTRL_PMCR_DIM_WID                    2
#define SYSCTRL_PMCR_DRCE0_WID                  1
#define SYSCTRL_PMCR_DRCE1_WID                  1
#define SYSCTRL_PMCR_DRCE2_WID                  1
#define SYSCTRL_PMCR_DRCE3_WID                  1
#define SYSCTRL_PMCR_RCLKON_WID                 1
#define SYSCTRL_PMCR_DCR_WID                    1
#define SYSCTRL_PMCR_REFCOUNTER_WID             11
#define SYSCTRL_PMCR_LO_WID                     1
#define SYSCTRL_PMCR_UP_WID                     1
#define SYSCTRL_PMCR_EM_WID                     1
#define SYSCTRL_PMCR_MC_WID                     1

//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------
// FMCR
#define SYSCTRL_FMCR_SDCS0_SEL_USE_CS2          0
#define SYSCTRL_FMCR_SDCS0_SEL_USE_CSD0         1

#define SYSCTRL_FMCR_SDCS1_SEL_USE_CS3          0
#define SYSCTRL_FMCR_SDCS1_SEL_USE_CSD1         1

#define SYSCTRL_FMCR_SLCDC_SEL_SLCDC            0
#define SYSCTRL_FMCR_SLCDC_SEL_BB               1

#define SYSCTRL_FMCR_NF_16BIT_SEL_8BIT          0
#define SYSCTRL_FMCR_NF_16BIT_SEL_16BIT         1

#define SYSCTRL_FMCR_NF_FMS_512B_PAGE           0
#define SYSCTRL_FMCR_NF_FMS_2KB_PAGE            1

#define SYSCTRL_FMCR_IOIS16_CTL_PC17_BOUT       0
#define SYSCTRL_FMCR_IOIS16_CTL_IOIS16          1

#define SYSCTRL_FMCR_PC_BVD2_CTL_PC18_BOUT      0
#define SYSCTRL_FMCR_PC_BVD2_CTL_PC_BVD2        1

#define SYSCTRL_FMCR_PC_BVD1_CTL_PC19_BOUT      0
#define SYSCTRL_FMCR_PC_BVD1_CTL_PC_BVD1        1

#define SYSCTRL_FMCR_PC_VS2_CTL_PC28_BOUT       0
#define SYSCTRL_FMCR_PC_VS2_CTL_PC_VS2          1

#define SYSCTRL_FMCR_PC_VS1_CTL_PC29_BOUT       0
#define SYSCTRL_FMCR_PC_VS1_CTL_PC_VS1          1

#define SYSCTRL_FMCR_PC_READY_CTL_PC30_BOUT     0
#define SYSCTRL_FMCR_PC_READY_CTL_PC_READY      1

#define SYSCTRL_FMCR_PC_WAIT_B_CTL_PC31_BOUT    0
#define SYSCTRL_FMCR_PC_WAIT_B_CTL_PC_WAIT_B    1

#define SYSCTRL_FMCR_KP_ROW6_CTL_PE1_ALT        0
#define SYSCTRL_FMCR_KP_ROW6_CTL_PE7_ALT        1

#define SYSCTRL_FMCR_KP_ROW7_CTL_PE2_ALT        0
#define SYSCTRL_FMCR_KP_ROW7_CTL_PE4_ALT        1

#define SYSCTRL_FMCR_KP_COL6_CTL_PE0_ALT        0
#define SYSCTRL_FMCR_KP_COL6_CTL_PE6_ALT        1

#define SYSCTRL_FMCR_UART4_RTS_CTL_PB31_AOUT    0
#define SYSCTRL_FMCR_UART4_RTS_CTL_PB26_ALT     1

#define SYSCTRL_FMCR_UART4_RXD_CTL_PB29_AOUT    0
#define SYSCTRL_FMCR_UART4_RXD_CTL_PB31_ALT     1

// GPCR
#define SYSCTRL_GPCR_CLK_DDR_MODE_IPP_DSE01     0
#define SYSCTRL_GPCR_CLK_DDR_MODE_SSTL_18       1

#define SYSCTRL_GPCR_DDR_MODE_IPP_DSE01         0
#define SYSCTRL_GPCR_DDR_MODE_SSTL_18           1

#define SYSCTRL_GPCR_CLOCK_GATING_EN_DISABLE    0
#define SYSCTRL_GPCR_CLOCK_GATING_EN_ENABLE     1

#define SYSCTRL_GPCR_DMA_BURST_OVERRIDE_BYPASS  0
#define SYSCTRL_GPCR_DMA_BURST_OVERRIDE_INCR    1

#define SYSCTRL_GPCR_PP_BURST_OVERRIDE_BYPASS   0
#define SYSCTRL_GPCR_PP_BURST_OVERRIDE_INCR     1

#define SYSCTRL_GPCR_USB_BURST_OVERRIDE_BYPASS  0
#define SYSCTRL_GPCR_USB_BURST_OVERRIDE_INCR    1

#define SYSCTRL_GPCR_ETM9_PAD_EN_DISABLE        0
#define SYSCTRL_GPCR_ETM9_PAD_EN_ENABLE         1

#define SYSCTRL_GPCR_BOOT_UART_USB1             0
#define SYSCTRL_GPCR_BOOT_UART_USB2             1
#define SYSCTRL_GPCR_BOOT_NF_8BIT_2KB_PAGE      2
#define SYSCTRL_GPCR_BOOT_NF_16BIT_2KB_PAGE     3
#define SYSCTRL_GPCR_BOOT_NF_16BIT_512B_PAGE    4
#define SYSCTRL_GPCR_BOOT_16BIT_CS0             5
#define SYSCTRL_GPCR_BOOT_32BIT_CS0             6
#define SYSCTRL_GPCR_BOOT_NF_8BIT_512B_PAGE     7

//DSCR
#define SYSCTRL_DSCR_DRIVING_STRENGTH_NORMAL 		0
#define SYSCTRL_DSCR_DRIVING_STRENGTH_HIGH 		1
#define SYSCTRL_DSCR_DRIVING_STRENGTH_MAX 		3

//PSCR
#define SYSCTRL_PSCR_100K_PD		0
#define SYSCTRL_PSCR_100K_PU		1
#define SYSCTRL_PSCR_47K_PU		2
#define SYSCTRL_PSCR_22K_PU		3

// PMCR
#define SYSCTRL_PMCR_DPTEN_DPTC_DISABLE         0
#define SYSCTRL_PMCR_DPTEN_DPTC_ENABLE          1

#define SYSCTRL_PMCR_DIE_DPTC_DISABLE           0
#define SYSCTRL_PMCR_DIE_DPTC_ENABLE            1

#define SYSCTRL_PMCR_DIM_DPTC_ALL               0
#define SYSCTRL_PMCR_DIM_DPTC_LOWER             1
#define SYSCTRL_PMCR_DIM_DPTC_UPPER             0
#define SYSCTRL_PMCR_DIM_DPTC_EMER              1

#define SYSCTRL_PMCR_DRCE_DISABLE               0
#define SYSCTRL_PMCR_DRCE_ENABLE                1

#define SYSCTRL_PMCR_RCLKON_DPTC_NORMAL         0
#define SYSCTRL_PMCR_RCLKON_DPTC_ALWAYS         1

#define SYSCTRL_PMCR_DCR_128_CLOCKS             0
#define SYSCTRL_PMCR_DCR_256_CLOCKS             1


#ifdef __cplusplus
}
#endif

#endif // __MX27_SYSCTRL_H__