mx27_pcmcia.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004,	MOTOROLA, INC. All Rights Reserved
// THIS SOURCE	CODE IS	CONFIDENTIAL AND PROPRIETARY AND MAY NOT
// BE USED	OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
// MOTOROLA, INC.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT 
//
//------------------------------------------------------------------------------
//
// Header:  mx27_pcmcia.h
//
// MX27 PCMCIA Controller register specific definitions
//
//------------------------------------------------------------------------------
#ifndef __MX27_PCMCIA_H
#define __MX27_PCMCIA_H


#if __cplusplus
extern "C" {
#endif

typedef struct{
	/* 0xD8004000 : PCMCIA registers */	
	REG32 PIPR;						// 00: PCMCIA Input Pin Register
	REG32 PSCR;						// 04: PCMCIA Status Change Register
	REG32 PER;						// 08: PCMCIA Enable Register
	REG32 PBR[7];					        // 0C-24: PCMCIA Base Register 6-0(for TO1.x), 4-0(for TO2 and later)
	REG32 POR[7];					        // 28-40: PCMCIA Option Register 6-0(for TO1.x), 4-0(for TO2 and later)
	REG32 POFR[7];					        // 44-5C: PCMCIA Offset Register 6-0(for TO1.x), 4-0(for TO2 and later)
	REG32 PGCR;						// 60: PCMCIA General Control Register
	REG32 PGSR;						// 64: PCMCIA General Status Register
}CSP_PCCARD_REGS, *PCSP_PCCARD_REGS;


//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------

// PCMCIA Input Pins Register(PIPR)
#define PCMCIA_PIPR_VS_LSH			0
#define PCMCIA_PIPR_WP_LSH			2
#define PCMCIA_PIPR_CD_LSH			3
#define PCMCIA_PIPR_BVD1_LSH			5
#define PCMCIA_PIPR_BVD2_LSH			6
#define PCMCIA_PIPR_RDY_LSH			7
#define PCMCIA_PIPR_POWERON_LSH			8

// PCMCIA Status Change Register(PSCR)
#define PCMCIA_PSCR_VSC1_LSH			0
#define PCMCIA_PSCR_VSC2_LSH			1
#define PCMCIA_PSCR_WPC_LSH			2
#define PCMCIA_PSCR_CDC1_LSH			3
#define PCMCIA_PSCR_CDC2_LSH			4
#define PCMCIA_PSCR_BVDC1_LSH			5
#define PCMCIA_PSCR_BVDC2_LSH			6
#define PCMCIA_PSCR_RDYL_LSH			7
#define PCMCIA_PSCR_RDYH_LSH			8
#define PCMCIA_PSCR_RDYF_LSH			9
#define PCMCIA_PSCR_RDYR_LSH			10
#define PCMCIA_PSCR_POWC_LSH			11

// PCMCIA Enable Register(PER)
#define PCMCIA_PER_VSE1_LSH			0
#define PCMCIA_PER_VSE2_LSH			1
#define PCMCIA_PER_WPE_LSH			2
#define PCMCIA_PER_CDCE1_LSH			3
#define PCMCIA_PER_CDCE2_LSH			4
#define PCMCIA_PER_BVDE1_LSH			5
#define PCMCIA_PER_BVDE2_LSH			6
#define PCMCIA_PER_RDYLE_LSH			7
#define PCMCIA_PER_RDYHE_LSH			8
#define PCMCIA_PER_RDYFE_LSH			9
#define PCMCIA_PER_RDYRE_LSH			10 
#define PCMCIA_PER_POWERONEN_LSH		11
#define PCMCIA_PER_ERRINTEN_LSH			12

//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------

// PCMCIA Input Pins Register(PIPR)
#define PCMCIA_PIPR_VS_WID			2
#define PCMCIA_PIPR_WP_WID			1
#define PCMCIA_PIPR_CD_WID			2
#define PCMCIA_PIPR_BVD1_WID			1
#define PCMCIA_PIPR_BVD2_WID			1
#define PCMCIA_PIPR_RDY_WID			1
#define PCMCIA_PIPR_POWERON_WID			1

// PCMCIA Status Change Register(PSCR)
#define PCMCIA_PSCR_VSC1_WID			1
#define PCMCIA_PSCR_VSC2_WID			1
#define PCMCIA_PSCR_WPC_WID			1
#define PCMCIA_PSCR_CDC1_WID			1
#define PCMCIA_PSCR_CDC2_WID			1
#define PCMCIA_PSCR_BVDC1_WID			1
#define PCMCIA_PSCR_BVDC2_WID			1
#define PCMCIA_PSCR_RDYL_WID			1
#define PCMCIA_PSCR_RDYH_WID			1
#define PCMCIA_PSCR_RDYF_WID			1
#define PCMCIA_PSCR_RDYR_WID			1
#define PCMCIA_PSCR_POWC_WID			1

// PCMCIA Enable Register(PER)
#define PCMCIA_PER_VSE1_WID			1
#define PCMCIA_PER_VSE2_WID			1
#define PCMCIA_PER_WPE_WID			1
#define PCMCIA_PER_CDCE1_WID			1
#define PCMCIA_PER_CDCE2_WID			1
#define PCMCIA_PER_BVDE1_WID			1
#define PCMCIA_PER_BVDE2_WID			1
#define PCMCIA_PER_RDYLE_WID			1
#define PCMCIA_PER_RDYHE_WID			1
#define PCMCIA_PER_RDYFE_WID			1
#define PCMCIA_PER_RDYRE_WID			1
#define PCMCIA_PER_POWERONEN_WID		1
#define PCMCIA_PER_ERRINTEN_WID			1



//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------

// PIPR Register Values
#define PCMCIA_PIPR_POWERON_ON			1
#define PCMCIA_PIPR_POWERON_DOWN		0

#define PCMCIA_PIPR_RDY_RDY			1
#define PCMCIA_PIPR_RDY_BUSY			0



/*********************************************************************
OTHER MACRO DEFINITIONS 
*********************************************************************/
// PIPR Register Values
// BVD2_STSCHG: Batt Voltage Detect2 in Mem mode, SPKR-In in IO mode
#define PCMCIA_PIPR_BVD2_SPKRIN			1

// BVD1_SPKRIN: Batt Voltage Detect1 in Mem mode, Status-Change in IO mode
#define PCMCIA_PIPR_BVD1_STSCHG			1


#ifdef __cplusplus
}
#endif

#endif // __MX27_PCMCIA_H