mx27_ddk.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

// DMA request resources.
//
//------------------------------------------------------------------------------
typedef enum {
    DMAC_REQUEST_RESERVED1,
    DMAC_REQUEST_CSPI3_RX_FIFO,
    DMAC_REQUEST_CSPI3_TX_FIFO,
    DMAC_REQUEST_Ext_DMA_REQ,
    DMAC_REQUEST_MSHC,
    DMAC_REQUEST_RESERVED2,
    DMAC_REQUEST_SDHC2,
    DMAC_REQUEST_SDHC1,
    DMAC_REQUEST_SSI2_RX0_FIFO,
    DMAC_REQUEST_SSI2_TX0_FIFO,
    DMAC_REQUEST_SSI2_RX1_FIFO,
    DMAC_REQUEST_SSI2_TX1_FIFO,
    DMAC_REQUEST_SSI1_RX0_FIFO,
    DMAC_REQUEST_SSI1_TX0_FIFO,
    DMAC_REQUEST_SSI1_RX1_FIFO,
    DMAC_REQUEST_SSI1_TX1_FIFO,
    DMAC_REQUEST_CSPI2_RX_FIFO,
    DMAC_REQUEST_CSPI2_TX_FIFO,
    DMAC_REQUEST_CSPI1_RX_FIFO,
    DMAC_REQUEST_CSPI1_TX_FIFO,
    DMAC_REQUEST_UART4_RX_FIFO,
    DMAC_REQUEST_UART4_TX_FIFO,
    DMAC_REQUEST_UART3_RX_FIFO,
    DMAC_REQUEST_UART3_TX_FIFO,
    DMAC_REQUEST_UART2_RX_FIFO,
    DMAC_REQUEST_UART2_TX_FIFO,
    DMAC_REQUEST_UART1_RX_FIFO,
    DMAC_REQUEST_UART1_TX_FIFO,
    DMAC_REQUEST_ATA_TX_FIFO,
    DMAC_REQUEST_ATA_RCV_FIFO,
    DMAC_REQUEST_CSI_STAT_FIFO,
    DMAC_REQUEST_CSI_RX_FIFO,
    DMAC_REQUEST_UART5_TX_FIFO,
    DMAC_REQUEST_UART5_RX_FIFO,
    DMAC_REQUEST_UART6_TX_FIFO,
    DMAC_REQUEST_UART6_RX_FIFO,
    DMAC_REQUEST_SDHC3,
    DMAC_REQUEST_NFC,
    DMAC_REQUEST_MAX = 64
} DMAC_REQUEST_SRC;
//------------------------------------------------------------------------------
//
// Type: DMAC_TRANSFER_STATUS
//
// DMA transfer status.
//
//------------------------------------------------------------------------------
typedef enum {
    DMAC_TRANSFER_STATUS_NONE,
    DMAC_TRANSFER_STATUS_COMPLETE=0x01,
    DMAC_TRANSFER_STATUS_BURST_TIMEOUT=0x02,
    DMAC_TRANSFER_STATUS_REQ_TIMEOUT=0x04,
    DMAC_TRANSFER_STATUS_ERROR=0x08,
    DMAC_TRANSFER_STATUS_BUFFER_OVERFLOW=0x10,
} DMAC_TRANSFER_STATUS;

//------------------------------------------------------------------------------
//
// Type: DMAC_TRANSFER_MODE
//
// DMA transfer mode.
//
//------------------------------------------------------------------------------
typedef enum {
    DMAC_TRANSFER_MODE_LINEAR_MEMORY,
    DMAC_TRANSFER_MODE_2D_MEMORY,
    DMAC_TRANSFER_MODE_FIFO,
    DMAC_TRANSFER_MODE_EOBE
} DMAC_TRANSFER_MODE;

//------------------------------------------------------------------------------
//
// Type: DMAC_TRANSFER_SIZE
//
// DMA transfer size.
//
//------------------------------------------------------------------------------
typedef enum DMAC_TRANSFER_SIZE {
    DMAC_TRANSFER_SIZE_32BIT,
    DMAC_TRANSFER_SIZE_8BIT,
    DMAC_TRANSFER_SIZE_16BIT
} DMAC_TRANSFER_SIZE;

//------------------------------------------------------------------------------
//
// Type: DMAC_REPEAT_TYPE
//
// DMA repeat type for DMA chain.
//
//------------------------------------------------------------------------------
typedef enum DMAC_REPEAT_TYPE {
    DMAC_REPEAT_DISABLED,
    DMAC_REPEAT_ONCE,
    DMAC_REPEAT_FOREVER, // dma cycle does not stop until TransStop() is called
} DMAC_REPEAT_TYPE;

//------------------------------------------------------------------------------
//
// Type: DMAC_CHANNEL_CFG 
//
// struct for DMA channel configurations.
//
//------------------------------------------------------------------------------
typedef struct DMAC_CHANNEL_CFG {
    UINT32               SrcAddr;
    UINT32               DstAddr;
    UINT32               DataSize;
    DMAC_TRANSFER_MODE   DstMode;
    DMAC_TRANSFER_MODE   SrcMode;
    BOOL                 MemDirIncrease;
    DMAC_TRANSFER_SIZE   DstSize;
    DMAC_TRANSFER_SIZE   SrcSize;
    DMAC_REPEAT_TYPE     RepeatType;
    BOOL                 ExtReqEnable;
    DMAC_REQUEST_SRC     ReqSrc;
    UINT32               BurstLength;
    BOOL                 ReqTimeout;
    UINT16               ReqTOCounter;
    UINT16               BusClkCounter;
    UINT16               WSR;
    UINT16               XSR;
    UINT16               YSR;
    UINT16               _pad;
} DMAC_CHANNEL_CFG,  *PDMAC_CHANNEL_CFG;


//------------------------------------------------------------------------------
//
// Structure and Macro for GPIO IOMUX configuration function DDKGpioEnable() 
// and DDKGpioDisable().
//
//------------------------------------------------------------------------------
typedef struct  {
    GPIO_CFG_TYPE   ConfigType;
    union {
        struct {
            GPIO_PORT   Port;
            UINT32      PinMap;
            UINT32      PuenMap;
        } PriConfig;
        struct {
            GPIO_PORT   Port;
            UINT32      PinMap;
            UINT32      PuenMap;
        } AltConfig;
        struct {
            GPIO_PORT               Port;
            UINT32                  InputPinMap;
            GPIO_INPUT_DEST_TYPE    InputDest;
            UINT32                  OutputPinMap;
            GPIO_OUTPUT_SOURCE_TYPE OutputSource;
            UINT32                  PuenMap;
        } ModuleIOConfig;
        struct {
            GPIO_PORT       Port;
            UINT32          PinMap;
            GPIO_INT_TYPE   IntType;    // interrupt trigger type
            DWORD           SysIntr;    // System interrupt ID
        } IntrConfig;
        struct {
            GPIO_PORT   Port;
            UINT32      InputPinMap;
            UINT32      OutputPinMap;
            UINT32      PuenMap;
        } IOConfig;
    };          
} DDK_GPIO_CFG, *PDDK_GPIO_CFG;

// The macro filling in DDK_GPIO_CFG structure.
#define DDK_GPIO_SET_CONFIG(config, module) \
    GPIOSetCfg2(GPIOValueCfgType(module), config, module)


//------------------------------------------------------------------------------
// Functions
BOOL DDKClockSetGatingMode(DDK_CLOCK_GATE_INDEX index, DDK_CLOCK_GATE_MODE mode);
BOOL DDKClockGetGatingMode(DDK_CLOCK_GATE_INDEX index, DDK_CLOCK_GATE_MODE *pMode);
BOOL DDKClockGetFreq(DDK_CLOCK_SIGNAL sig, UINT32 *freq);
BOOL DDKClockConfigBaud(DDK_CLOCK_SIGNAL sig, DDK_CLOCK_BAUD_SOURCE src, UINT32 div);
BOOL DDKClockSetCKO(BOOL bEnable, DDK_CLOCK_CKO_SRC src, DDK_CLOCK_CKO_DIV div);

BOOL DDKGpioEnable(DDK_GPIO_CFG *pGpioCfg);
BOOL DDKGpioDisable(DDK_GPIO_CFG *pGpioCfg);
BOOL DDKGpioWriteData(GPIO_PORT port, UINT32 portMask, UINT32 data);
BOOL DDKGpioWriteDataPin(GPIO_PORT port, UINT32 pin, UINT32 data);
BOOL DDKGpioReadData(GPIO_PORT port, UINT32 portMask, UINT32 *pData);
BOOL DDKGpioReadDataPin(GPIO_PORT port, UINT32 pin, UINT32 *pData);
BOOL DDKGpioReadIntr(GPIO_PORT port, UINT32 portMask, UINT32 *pStatus);
BOOL DDKGpioReadIntrPin(GPIO_PORT port, UINT32 pin, UINT32 *pStatus);
BOOL DDKGpioClearIntrPin(GPIO_PORT port, UINT32 pin);
BOOL DDKGpioSetIntrPin(GPIO_PORT port, UINT32 pin, BOOL bEnable);
BOOL DDKGpioSetIntrType(GPIO_PORT port, UINT32 pin, GPIO_INT_TYPE type);

UINT8 DDKDmacRequestChan(UINT8 chan);
BOOL DDKDmacReleaseChan(UINT8 chan);
UINT8 DDKDmacConfigureChan(UINT8 chan, DMAC_CHANNEL_CFG *pChannelCfg);
BOOL DDKDmacStartChan(UINT8 chan);
BOOL DDKDmacStopChan(UINT8 chan);
UINT32 DDKDmacGetTransStatus(UINT8 chan);
UINT32 DDKDmacGetTransSize(UINT8 chan);
void DDKDmacSetSrcAddress(UINT8 chan, UINT32 src);
void DDKDmacSetDestAddress(UINT8 chan, UINT32 dest);
void DDKDmacSetTransCount(UINT8 chan, UINT32 count);
void DDKDmacSetBurstLength(UINT8 chan, UINT32 burstLen);
void DDKDmacSetRepeatType(UINT8 chan, DMAC_REPEAT_TYPE repeatType);
BOOL DDKDmacIsChannelIntr(UINT8 chan);
void DDKDmacClearChannelIntr(UINT8 chan);
void DDKDmacEnableChannelIntr(UINT8 chan);
void DDKDmacDisableChannelIntr(UINT8 chan);

#endif // __MX27_DDK_H__