mx27_ddk.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: mx27_ddk.h
//
// Contains MX27 definitions to assist with driver development.
//
//------------------------------------------------------------------------------
#ifndef __MX27_DDK_H__
#define __MX27_DDK_H__

//------------------------------------------------------------------------------
// GENERAL CONSTANTS
//
//------------------------------------------------------------------------------
#define DMAC_CHANNEL_INVALID         -1

//------------------------------------------------------------------------------
// Types
//
//-----------------------------------------------------------------------------
//
// Type: DDK_CLOCK_SIGNAL
//
// Clock signal name for querying/setting clock configuration.
//
//-----------------------------------------------------------------------------
typedef enum
{
    DDK_CLOCK_SIGNAL_MPLL               = 0,
    DDK_CLOCK_SIGNAL_SPLL               = 1,
    DDK_CLOCK_SIGNAL_ARM                = 2,
    DDK_CLOCK_SIGNAL_AHB                = 3,
    DDK_CLOCK_SIGNAL_IPG                = 4,
    DDK_CLOCK_SIGNAL_PERDIV1            = 5,
    DDK_CLOCK_SIGNAL_PERDIV2            = 6,
    DDK_CLOCK_SIGNAL_PERDIV3            = 7,
    DDK_CLOCK_SIGNAL_PERDIV4            = 8,
    DDK_CLOCK_SIGNAL_NFC                = 9,
    DDK_CLOCK_SIGNAL_USB                = 10,
    DDK_CLOCK_SIGNAL_SSI1               = 11,
    DDK_CLOCK_SIGNAL_SSI2               = 12,
    DDK_CLOCK_SIGNAL_H264               = 13,
    DDK_CLOCK_SIGNAL_MSHC               = 14,
    DDK_CLOCK_SIGNAL_CSI                = 15,
    DDK_CLOCK_SIGNAL_ENUM_END           = 16
    } DDK_CLOCK_SIGNAL;

//------------------------------------------------------------------------------
//
// Type: DDK_CLOCK_GATE_INDEX
//
// Index for referencing the corresponding clock gating control bits within
// the CCM.
//
//------------------------------------------------------------------------------
typedef enum 
{
    DDK_CLOCK_GATE_INDEX_SSI2           = 0,
    DDK_CLOCK_GATE_INDEX_SSI1           = 1,
    DDK_CLOCK_GATE_INDEX_SLCDC          = 2,
    DDK_CLOCK_GATE_INDEX_SDHC3          = 3,
    DDK_CLOCK_GATE_INDEX_SDHC2          = 4,
    DDK_CLOCK_GATE_INDEX_SDHC1          = 5,
    DDK_CLOCK_GATE_INDEX_SCC            = 6,
    DDK_CLOCK_GATE_INDEX_SAHARA         = 7,
    DDK_CLOCK_GATE_INDEX_RTIC           = 8,
    DDK_CLOCK_GATE_INDEX_RTC            = 9,
    DDK_CLOCK_GATE_INDEX_RESERVE1       = 10,
    DDK_CLOCK_GATE_INDEX_PWM            = 11,
    DDK_CLOCK_GATE_INDEX_OWIRE          = 12,
    DDK_CLOCK_GATE_INDEX_MSHC           = 13,
    DDK_CLOCK_GATE_INDEX_LCDC           = 14,
    DDK_CLOCK_GATE_INDEX_KPP            = 15,
    DDK_CLOCK_GATE_INDEX_IIM            = 16,
    DDK_CLOCK_GATE_INDEX_I2C2           = 17,
    DDK_CLOCK_GATE_INDEX_I2C1           = 18,
    DDK_CLOCK_GATE_INDEX_GPT6           = 19,
    DDK_CLOCK_GATE_INDEX_GPT5           = 20,
    DDK_CLOCK_GATE_INDEX_GPT4           = 21,
    DDK_CLOCK_GATE_INDEX_GPT3           = 22,
    DDK_CLOCK_GATE_INDEX_GPT2           = 23,
    DDK_CLOCK_GATE_INDEX_GPT1           = 24,
    DDK_CLOCK_GATE_INDEX_GPIO           = 25,
    DDK_CLOCK_GATE_INDEX_FEC            = 26,
    DDK_CLOCK_GATE_INDEX_EMMA           = 27,
    DDK_CLOCK_GATE_INDEX_DMA            = 28,
    DDK_CLOCK_GATE_INDEX_CSPI3          = 29,
    DDK_CLOCK_GATE_INDEX_CSPI2          = 30,
    DDK_CLOCK_GATE_INDEX_CSPI1          = 31,
    DDK_CLOCK_GATE_INDEX_RESERVE2       = 32,
    DDK_CLOCK_GATE_INDEX_RESERVE3       = 33,
    DDK_CLOCK_GATE_INDEX_MSHC_BAUD      = 34,
    DDK_CLOCK_GATE_INDEX_NFG_BAUD       = 35,
    DDK_CLOCK_GATE_INDEX_SSI2_BAUD      = 36,
    DDK_CLOCK_GATE_INDEX_SSI1_BAUD      = 37,
    DDK_CLOCK_GATE_INDEX_H264_BAUD      = 38,
    DDK_CLOCK_GATE_INDEX_PERCLK4        = 39,
    DDK_CLOCK_GATE_INDEX_PERCLK3        = 40,
    DDK_CLOCK_GATE_INDEX_PERCLK2        = 41,
    DDK_CLOCK_GATE_INDEX_PERCLK1        = 42,
    DDK_CLOCK_GATE_INDEX_HCLK_USB       = 43,
    DDK_CLOCK_GATE_INDEX_HCLK_SLCDC     = 44,
    DDK_CLOCK_GATE_INDEX_HCLK_SAHARA    = 45,
    DDK_CLOCK_GATE_INDEX_HCLK_RTIC      = 46,
    DDK_CLOCK_GATE_INDEX_HCLK_LCDC      = 47,
    DDK_CLOCK_GATE_INDEX_HCLK_H264      = 48,
    DDK_CLOCK_GATE_INDEX_HCLK_FEC       = 49,
    DDK_CLOCK_GATE_INDEX_HCLK_EMMA      = 50,
    DDK_CLOCK_GATE_INDEX_HCLK_EMI       = 51,
    DDK_CLOCK_GATE_INDEX_HCLK_DMA       = 52,
    DDK_CLOCK_GATE_INDEX_HCLK_CSI       = 53,
    DDK_CLOCK_GATE_INDEX_HCLK_BROM      = 54,
    DDK_CLOCK_GATE_INDEX_HCLK_ATA       = 55,
    DDK_CLOCK_GATE_INDEX_WDT            = 56,
    DDK_CLOCK_GATE_INDEX_USB            = 57,
    DDK_CLOCK_GATE_INDEX_UART6          = 58,
    DDK_CLOCK_GATE_INDEX_UART5          = 59,
    DDK_CLOCK_GATE_INDEX_UART4          = 60,
    DDK_CLOCK_GATE_INDEX_UART3          = 61,
    DDK_CLOCK_GATE_INDEX_UART2          = 62,
    DDK_CLOCK_GATE_INDEX_UART1          = 63,
} DDK_CLOCK_GATE_INDEX;

//------------------------------------------------------------------------------
//
// Type: DDK_CLOCK_GATE_MODE
//
// Clock gating modes supported by CCM clock gating registers.
//
//------------------------------------------------------------------------------
typedef enum {
    DDK_CLOCK_GATE_MODE_DISABLE         = 0,
    DDK_CLOCK_GATE_MODE_ENABLE          = 1,
} DDK_CLOCK_GATE_MODE;

//------------------------------------------------------------------------------
//
//  Type: DDK_CLOCK_BAUD_SOURCE
//
//  Input source for baud clock generation.
//
//------------------------------------------------------------------------------
typedef enum {
    DDK_CLOCK_BAUD_SOURCE_SPLL        = 0,
    DDK_CLOCK_BAUD_SOURCE_MPLL        = 1,
} DDK_CLOCK_BAUD_SOURCE;

//------------------------------------------------------------------------------
//
// Type: DDK_CLOCK_CKO_SRC
//
// Clock output source (CKO) signal selections.
//
//------------------------------------------------------------------------------
typedef enum {
    DDK_CLOCK_CKO_SRC_CLK32             = 0,
    DDK_CLOCK_CKO_SRC_PREMCLK           = 1,
    DDK_CLOCK_CKO_SRC_CLK26M            = 2,
    DDK_CLOCK_CKO_SRC_MPLL_REF_CLK      = 3,
    DDK_CLOCK_CKO_SRC_SPLL_REF_CLK      = 4,
    DDK_CLOCK_CKO_SRC_MPLL_CLK          = 5,
    DDK_CLOCK_CKO_SRC_SPLL_CLK          = 6,
    DDK_CLOCK_CKO_SRC_FCLK              = 7,
    DDK_CLOCK_CKO_SRC_HCLK              = 8,
    DDK_CLOCK_CKO_SRC_IPGCLK            = 9,
    DDK_CLOCK_CKO_SRC_PERCLK1           = 10,
    DDK_CLOCK_CKO_SRC_PERCLK2           = 11,
    DDK_CLOCK_CKO_SRC_PERCLK3           = 12,
    DDK_CLOCK_CKO_SRC_PERCLK4           = 13,
    DDK_CLOCK_CKO_SRC_SSI1_BAUD         = 14,
    DDK_CLOCK_CKO_SRC_SSI2_BAUD         = 15,
    DDK_CLOCK_CKO_SRC_NFC_BAUD          = 16,
    DDK_CLOCK_CKO_SRC_MSHC_BAUD         = 17,
    DDK_CLOCK_CKO_SRC_H264_BAUD         = 18,
    DDK_CLOCK_CKO_SRC_CLK60M_ALWAYS     = 19,
    DDK_CLOCK_CKO_SRC_CLK32K_ALWAYS     = 20,
    DDK_CLOCK_CKO_SRC_CLK48M            = 21,
    DDK_CLOCK_CKO_SRC_DPTC_REF_CLK      = 22
} DDK_CLOCK_CKO_SRC;

//------------------------------------------------------------------------------
//
// Type: DDK_CLOCK_CKO_DIV
//
// Clock output source (CKO) divider selections.
//
//------------------------------------------------------------------------------
typedef enum {
    DDK_CLOCK_CKO_DIV_1                 = 0,
    DDK_CLOCK_CKO_DIV_2                 = 1,
    DDK_CLOCK_CKO_DIV_3                 = 2,
    DDK_CLOCK_CKO_DIV_4                 = 3,
    DDK_CLOCK_CKO_DIV_5                 = 4,
    DDK_CLOCK_CKO_DIV_6                 = 5,
    DDK_CLOCK_CKO_DIV_7                 = 6,
    DDK_CLOCK_CKO_DIV_8                 = 7,
} DDK_CLOCK_CKO_DIV;

//------------------------------------------------------------------------------
//
// Type: DMAC_REQUEST_SRC
//