mx27_usb.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

                        // FS idle.
                        // This field is zero if Port Power(PP) is zero in host mode.
                        // This bit is not-EHCI compatible.
                        // In Device mode:
                        // After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller
                        // will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal
                        // operation. Also, when this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is also set to one.
    unsigned int SUSP:1;    //In Host Mode: Read/Write. 1=Port in suspend state. 0=Port not in suspend state. Default=0.
                        // Port Enabled Bit and Suspend bit of this register define the port states as follows:
                        // Bits [Port Enabled, Suspend]Port State
                        // 0x Disable
                        // 10 Enable
                        // 11 Suspend
                        // When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction
                        // if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not
                        // change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.
                        // The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit.
                        // If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined.
                        // This field is zero if Port Power(PP) is zero in host mode.
                        // In Device Mode: Read Only. 1=Port in suspend state. 0=Port not in suspend state. Default=0.
                        // In device mode this bit is a read only status bit.
                        
    unsigned int PR:1;      //Port Reset
                        // This field is zero if Port Power(PP) is zero. 
                        // In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0.
                        // When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to
                        // zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
                        // duration is timed in the driver.
                        // In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
    unsigned int HSP:1; //High-Speed Port — Read Only. Default = 0b.
                        // When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a
                        // high-speed mode.
                        // Note: HSP is redundant with PSPD(27:26) but will remain in the design for compatibility.
                        //This bit is not defined in the EHCI specification.
    unsigned int LS:2;      //Line Status—Read Only. 
                        // These bits reflect the current logical levels of the D+(bit 11) and D- (bit 10) signal lines. The encoding of the bits are:
                        //  Bits [11:10]Meaning
                        //  00b SE0
                        //  10b J-state
                        //  01b K-state
                        //  11b Undefined
                        // In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing
                        // manage the connection of LS and FS.
                        // In device mode, the use of linestate by the device controller driver is not necessary
    unsigned int PP:1;      //Port Power (PP)—Read/Write or Read Only. 
                        // The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS
                        // register. The behavior is as follows:
                        //  PPC         PP      Operation
                        //  0b      0b      Read Only— A device controller with no OTG capability does not have port power control switches.
                        //  1b      1b/0b C  RW. Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on).
                        // When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
                        // When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller
                        // driver from a one to a zero (removing power from the port).
                        // This feature is implemented in the host/OTG controller (PPC = 1).In a device only implementation port power control is not necessary, thus PPC and PP =0
    unsigned int PO:1;      //Port Owner—Read/Write. Default = 0. 
                        // This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1 transition.
                        // This bit unconditionally goes to 1 whenever the Configured bit is zero System software uses this field to release ownership of the port to a selected host
                        // controller (in the event that the attached device is not a high-speed device).
                        // Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that an internal companion controller owns and
                        // controls the port.
                        // Port owner handoff is not implemented in this design, therefore this bit will always be 0.
    unsigned int PIC:2; //Port Indicator Control — Read/Write. Default = Ob. 
                        // Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is a zero. If
                        // P_INDICATOR bit is a one, then the bit is:
                        //  00b Port indicators are off
                        //  01b Amber
                        //  10b Green
                        //  11b Undefined
                        // Refer to the USB Specification Revision 2.0 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel, Lucent, Microsoft,
                        // NEC, Philips. http://www.usb.org for a description on how these bits are to be used.
                        // This field is output from the controller as signals port_ind_ctl_1 & port_ind_ctl_0 for use by an external led driving circuit
                        
    unsigned int PTC:4; //Port Test Control — Read/Write. Default = 0000b. 
                        // Any other value than zero indicates that the port is operating in test mode.
                        // ValueSpecific Test
                        //  0000bTEST_MODE_DISABLE
                        //  0001bJ_ STATE
                        //  0010bK_STATE
                        //  0011bSE0 (host) / NAK (device)
                        //  0100bPacket
                        //  0101bFORCE_ENABLE_HS
                        //  0110bFORCE_ENABLE_FS
                        //  0111bFORCE_ENABLE_LS
                        //  1000b to 1111bReserved
                        // Refer to Chapter 7 of the USB Specification Revision 2.0 Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel,
                        // Lucent, Microsoft, NEC, Philips. http://www.usb.org for details on each test mode.
                        // The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any
                        // of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back
                        // to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point.
                        // Note: Low speed operations are not supported as a peripheral device
    unsigned int WKCN:1;    //Wake on Connect Enable (WKCNNT_E) — Read/Write. Default=0b. 
                        //Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.
                        // This field is zero if Port Power(PP) is zero or in device mode.
                        // This bit is output from the controller as signal pwrctl_wake_dscnnt_en (OTG/host core only) for use by an external power control circuit. 
    unsigned int WKDC:1;   //Wake on Disconnect Enable (WKDSCNNT_E) — Read/Write. Default=0b.
                        //Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.
                        // This field is zero if Port Power(PP) is zero or in device mode.
                        // This bit is output from the controller as signal pwrctl_wake_dscnnt_en (OTG/host core only) for use by an external power control circuit
    unsigned int WKOC:1;    //Wake on Over-current Enable (WKOC_E) — Read/Write.Default = 0b.
                        // Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events.
                        // This field is zero if Port Power(PP) is zero. 
                        // This bit is output from the controller as signal pwrctl_wake_ovrcurr_en (OTG/host core only) for use by an external power control circuit.
    unsigned int PHCD:1;    // PHY Low Power Suspend - Clock Disable (PLPSCD) – Read/Write. Default= 0b. 
                        // Writing this bit to a 1b will disable the PHY clock. Writing a 0b enables it. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock
                        // cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend – Clock Disable
                        // when the device is not running (USBCMD Run/Stop=0b) or the host has signaled suspend (PORTSC SUSPEND=1b). Low power suspend will be
                        // cleared automatically when the host has signaled resume if using a circuit similar to that in . Before forcing a resume from the device, the device controller
                        // driver must clear this bit.
                        // In host mode, the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no
                        // downstream device is connected. Low power suspend is completely under the control of software.
                        // See for more discussion on clock disable and power down issues.
                        // This bit is not defined in the EHCI specification.
                        
    unsigned int PFSC:1;    //Port Force Full Speed Connect – Read/Write. Default = 0b. 
                        // Writing this bit to a 1b will force the port to only connect at Full Speed. It disables the chirp
                        // sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
                        // This bit is not defined in the EHCI specification.
                        // This bit is for debugging purposes.
    unsigned int R:1;       //Reserved. These bits are reserved and should be set to zero.
    unsigned int PSPD:2;    //Port Speed – Read Only.  
                        // This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS
                        // operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing
                        // steers data to the Protocol Engine w/ Embedded Transaction Translator.
                        // 00 – Full Speed
                        // 01 – Low Speed
                        // 10 – High Speed
                        //This bit is not defined in the EHCI specification.
    unsigned int PTW:1; //Parallel Transceiver Width – Read/Write. 
                        // This register bit is used in conjunction with the configuration constant VUSB_HS_PHY8_16 to control
                        // whether the data bus width of the UTMI transceiver interface. If VUSB_HS_PHY8_16 is set for 0 or 1 then this bit is read only. If
                        // VUSB_HS_PHY8_16 is 2 or 3 then this bit is read/write. This bit is reset to 1 if VUSB_HS_PHY8_16 selects a default UTMI interface width of 16-bits else it is
                        // reset to 0.
                        // Writing this bit to 0 selects the 8-bit [60MHz] UTMI interface.
                        // Writing this bit to 1 selects the 16-bit [30MHz] UTMI interface.
                        // This bit has no effect if the Philips or Serial interfaces are selected.
                        // This bit is not defined in the EHCI specification.
    unsigned int STS:1; //Serial Transceiver Select – Read/Write. 
                        // This register bit is used in conjunction with the configuration constant VUSB_HS_PHY_SERIAL to control
                        // whether the parallel or serial transceiver interface is selected for FS and LS operation. The Serial Interface Engine can be used in combination with the
                        // UTMI+ or ULPI physical inte