mx27_usb.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

    unsigned int UEE:1;     // USB Error Interrupt Enable
                            // When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the
                            // next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register.
    unsigned int PCE:1;     //Port Change Detect Enable
                            // When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue
                            // an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit.
    unsigned int FRE:1;     // Frame List Rollover Enable
                            // When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an
                            // interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
                            // Only used by the host controller.
    unsigned int SEE:1;     //System Error Enable
                            // When this bit is a one, and the System Error bit in the USBSTS register is a one, the host/device controller will issue an
                            // interrupt. The interrupt is acknowledged by software clearing the System Error bit.
    unsigned int AAE:1;     //Interrupt on Async Advance Enable
                            // When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue
                            // an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.
                            // Only used by the host controller.
    unsigned int URE:1;     //USB Reset Enable
                            //When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an
                            // interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit.
                            //Only used by the device controller.
    unsigned int SRE:1;     // SOF Received Enable
                            // When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an
                            // interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.
    unsigned int SLE:1;     //Sleep Enable 
                            // When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt.
                            // The interrupt is acknowledged by software writing a one to the DCSuspend bit.
                            // Only used by the device controller.
    unsigned int R:1;           //Reserved. These bits are reserved and should be set to zero.
    unsigned int ULPIE:1;       //ULPI Enable 
                            // When this bit is a one, and the ULPI Interrupt bit in the USBSTS register transitions, the controller will issue and interrupt. The
                            // interrupt is acknowledged by software writing a one to the ULPI Interrupt bit.
                            // Used by both host & device controller. Only present in designs where configuration constant VUSB_HS_PHY_ULPI = 1.
    unsigned int RESERVED:21; //Reserved. These bits are reserved and should be set to zero.
}USB_USBINTR_T;

typedef struct _USB_BURSTSIZE {
    unsigned int RXPBURST:8;    //Programmable RX Burst Length. (Read/Write) Default is the constant VUSB_HS_RX_BURST. 
                            // This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory.
    unsigned int TXPBURST:8;    // Programmable TX Burst Length. (Read/Write) Default is the constant VUSB_HS_TX_BURST. 
                            // This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus.
    unsigned int RESERVED:24; //Reserved. These bits are reserved and should be set to zero.
}USB_BURSTSIZE_T;       //Read/Write (Writes must be DWord Writes)

typedef struct _USB_TXFILLTUNING {//The fields in this register control performance tuning associated with how the host controller posts data to
                                     //the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance include
                                     //the how much data to post into the FIFO and an estimate for how long that operation should take in the target system.    unsigned int TXSCHOH:8;
    unsigned int TXSCHEALTH:5;
    unsigned int RESERVED:3;    //Reserved. These bits are reserved and should be set to zero.
    unsigned int TXFIFOTHRES:6;
    unsigned int RESERVED2:10;  //Reserved. These bits are reserved and should be set to zero.
}USB_TXFILLTUNING_T;    // Default:00020000h Read/Write (Writes must be DWord Writes)


typedef struct _USB_ULPI_VIEWPORT { //The register provides indirect access to the ULPI PHY register set. Although the core performs access to
                                        // the ULPI PHY register set, there may be extraordinary circumstances where software may need direct access.
    unsigned int ULPIDATWR:8;   //ULPI Data Write . Read/Write. 
                            // When a write operation is commanded, the data to be sent is written to this field.
    unsigned int ULPIDATRD:8; //ULPI Data Read . Read Only. 
                            // After a read operation completes, the result is placed in this field
    unsigned int ULPIADDR:8;    //ULPI Data Address . Read/Write. 
                            // When a read or write operation is commanded, the address of the operation is written to  this field.
    unsigned int ULPIPORT:3;    // ULPI Port Number – Read/Write. For the wakeup or read/write operation to be executed, this value selects the port number the ULPI PHY is
                            // attached to in the multi-port host. The range is 0 to 7. This field should always be written as a 0 for the non-multi port products.
    unsigned int ULPISS:1;      //ULPI Sync State – Read Only. 
                            // (1) – Normal Sync. State. (0) In another state (ie. carkit, serial, low power) This bit represents the state of the ULPI
                            // interface. Before reading this bit, the ULPIPORT field should be set accordingly if used with the multi-port host. Otherwise, this field should
                            // always remain 0.
    unsigned int R:1;           //Reserved. These bits are reserved and should be set to zero.
    unsigned int ULPIRW:1;  // ULPI Read/Write Control – Read/Write. 
                            // (0) – Read; (1) – Write. This bit selects between running a read or write operation.
    unsigned int ULPIRUN:1; // ULPI Read/Write Run – Read/Write. 
                            // Writing the '1' to this bit will begin the read/write operation. The bit will automatically transition to 0 after the
                            // read/write is complete. Once this bit is set, the driver can not set it back to'0'.
                            // Note: The driver must never executue a wakeup and a read/write operation at the same time.
    unsigned int ULPIWU:1;  //ULPI Wakeup – Read/Write. 
                            // Writing the'1' to this bit will begin the wakeup operation. The bit will automatically transition to 0 after the
                            // wakeup is complete. Once this bit is set, the driver can not set it back to '0'.
}USB_ULPI_VIEWPORT_T;

typedef struct _USB_PORTSC { 
    unsigned int CCS:1; //Current Connect Status—Read Only.
                        // In Host Mode:
                        // 1=Device is present on port. 
                        // 0=No device is present. Default = 0.
                        // This value reflects the current state of the port, and may not correspond directly to the
                        // event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PP) is zero in host mode.
                        // In Device Mode:
                        // 1=Attached. 
                        // 0=Not Attached. Default=0. 
                        // A one indicates that the device successfully attached and is operating in either high speed or full speed as
                        // indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software
                        // writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended   
    unsigned int CSC:1; //Connect Status Change—R/WC. 
                        // 1 =Change in Current Connect Status.
                        // 0=No change. Default 0.
                        // In Host Mode:
                        // Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect
                        // status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system
                        // software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a
                        // one to it.
                        // This field is zero if Port Power(PP) is zero in host mode.
                        // In Device Mode:
                        // This bit is undefined in device controller mode.
    unsigned int PE:1;      //Port Enabled/Disabled—Read/Write. 1=Enable. 0=Disable. Default 0.
                        // In Host Mode:
                        //Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can
                        // be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port
                        // state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.
                        // When the port is disabled, (0b) downstream propagation of data is blocked except for reset.
                        // This field is zero if Port Power(PP) is zero in host mode.
                        // In Device Mode:
                        // The device port is always enabled. (This bit will be one)
    unsigned int PEC:1; //Port Enable/Disable Change—R/WC. 
                        // 1=Port enabled/disabled status has changed. 
                        // 0=No change. Default = 0.
                        // In Host Mode:
                        // For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2
                        // point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it.
                        // This field is zero if Port Power(PP) is zero.
                        // In Device mode:
                        // The device port is always enabled. (This bit will be zero).
    unsigned int OCA:1; //Over-current Active—Read Only. Default 0. 
                        // 1=This port currently has an over-current condition. 
                        // 0=This port does not have an over-current condition.
                        // This bit will automatically transition from one to zero when the over current condition is removed.
                        // For host/OTG implementations the user can provide over-current detection to the vbus_pwr_fault input for this condition.
                        // For device-only implementations this bit shall always be 0.
    unsigned int OCC:1; // Over-current Change—R/WC. Default=0. 
                        // 1=This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a
                        //  one to this bit position. For host/OTG implementations the user can provide over-current detection to
                        // the vbus_pwr_fault input for this condition.
                        //For device-only implementations this bit shall always be 0.
    unsigned int FPR:1; //Force Port Resume —Read/Write. 1= Resume detected/driven on port. 0=No
                        //resume (K-state) detected/driven on port. Default = 0.
                        //In Host Mode:
                        // Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend
                        // state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit
                        // will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to
                        // set this bit to a zero after the rsume duration is timed in the driver.
                        // Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The
                        // resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the
                        // high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or