mx27_usb.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

                            // Valuesmeaning
                            // 0 Do not process the Periodic Schedule
                            // 1 Use the PERIODICLISTBASE register to access the PeriodicSchedule.
                            // Only the host controller uses this bit.
    unsigned int ASE:1;     //Asynchronous Schedule Enable — Read/Write. Default 0b. 
                            // This bit controls whether the host controller skips processing the Asynchronous Schedule.
                            // Valuesmeaning
                            // 0 Do not process the Asynchronous Schedule.
                            // 1 Use the ASYNCLISTADDR register to access theAsynchronous Schedule.
                            // Only the host controller uses this bit.
    unsigned int IAA:1;     //Interrupt on Async Advance Doorbell — Read/Write. 
                            // This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time
                            // it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
                            // When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the
                            // Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold.
                            // The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write
                            // a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results.
                            // This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results.
    unsigned int LR:1;          //Light Host/Device Controller Reset (OPTIONAL) — Read Only. 
                            // Not Implemented. This field will always be "0".

    unsigned int ASP:2;     //Asynchronous Schedule Park Mode Count (OPTIONAL) . Read/Write. 
                            //If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is RO. It contains
                            // a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before
                            // continuing traversal of the Asynchronous schedule. See Section 4.10.3.2 for full operational details. Valid values are 1h to 3h. Software must not write a zero to this bit
                            // when Park Mode Enable is a one as this will result in undefined behavior. 
                            //This field is set to 3h in this implementation.
    unsigned int R1:1;          //Reserved. These bits are reserved and should be set to zero.
    unsigned int ASPE:1;        //Asynchronous Schedule Park Mode Enable (OPTIONAL) . Read/Write.
                            // If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO.
                            // Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.
                            // This field is set to "1" in this implementation.
    unsigned int ATDTW:1;       //Add dTD TripWire – Read/Write. [device mode only]
                            // This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed)
                            // endpoint’s linked list. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state machine is hazard region for which
                            // adding a dTD to a primed endpoint may go unrecognized. For more information on the use of this bit, see the Device Operational Model section of
                            // the ARC USB-HS OTG High-Speed USB On-The-Go DEV reference manual.
    unsigned int SUTW:1;        // Setup TripWire – Read/Write. [device mode only] 
                            // This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from
                            // a QH by the DCD without being corrupted. If the setup lockout mode is off (See USBMODE) then there exists a hazard when new setup data arrives while the
                            // DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware
                            // when a hazard exists. For more information on the use of this bit, see the Device Operational Model section of the ARC USB-HS OTG High-Speed USB
                            // On-The-Go DEV reference manual.
    unsigned int R2:1;          //Reserved. These bits are reserved and should be set to zero.
    unsigned int FS2:1;     //

    unsigned int ITC:8;     //Interrupt Threshold Control —Read/Write. Default 08h. 
                            //The system software uses this field to set the maximum rate at which the host/device
                            // controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below.
                            // ValueMaximum Interrupt Interval
                            // 00h Immediate (no threshold)
                            // 01h 1 micro-frame
                            // 02h 2 micro-frames
                            // 04h 4 micro-frames
                            // 08h 8 micro-frames
                            // 10h 16 micro-frames
                            // 20h 32 micro-frames
                            // 40h 64 micro-frames
    unsigned int RESERVED:8;    //Reserved. These bits are reserved and should be set to zero.
    
}USB_USBCMD_T;

typedef struct _USB_USBSTS{
    unsigned int UI:1;          //USB Interrupt (USBINT) — R/WC. 
                            // This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the
                            // Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is
                            // detected. A short packet is when the actual number of bytes received was less than the expected number of bytes.
    unsigned int UEI:1;     //USB Error Interrupt (USBERRINT) — R/WC. 
                            // When completion of a USB transaction results in an error condition, this bit is set by the Host/Device
                            // Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set
                            // See Section (Reference Host Operation Model: Transfer/Transaction Based Interrupt – i.e. 4.15.1 in EHCI Enhanced Host Controller Interface Specification
                            // for Universal Serial Bus, Revision 0.95, November 2000, Intel Corporation. http://www.intel.com) for a complete list of host error interrupt conditions.
                            // See section Device Error Matrix in the ARC USB-HS OTG High-Speed USB On-The-Go DEV reference manual.
                            // The device controller detects resume signaling only.
    unsigned int PCI:1;     //Port Change Detect — R/WC. 
                            // The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or
                            // the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
                            // The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or
                            // high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively.
                            // This bit is not EHCI compatible.
    unsigned int FRI:1;     // Frame List Rollover — R/WC. 
                            // The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value
                            // at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USBCMD
                            // register) is 1024, the Frame Index Register rolls over every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one
                            // every time FHINDEX [12] toggles.
                            // Only used by the host controller.
    unsigned int SEI:1;     //System Error— R/WC. 
                            // This bit is not used in this implementation and will always be set to "0".
    unsigned int AAI:1;     //Interrupt on Async Advance — R/WC. 0=Default. 
                            // System software can force the host controller to issue an interrupt the next time the host controller
                            // advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the
                            // assertion of that interrupt source.
                            //Only used by the host controller.
    unsigned int URI:1;     // USB Reset Received – R/WC. 0=Default. 
                            // When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software
                            // can write a 1 to this bit to clear the USB Reset Received status bit.
                            // Only used by the device controller.
    unsigned int SRI:1;     //SOF Received – R/WC. 0=Default. 
                            // When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the
                            // device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode
                            // and every 125ms in HS mode and will be synchronized to the actual SOF that is received.
                            // Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.
                            // In host mode, this bit will be set every 125us and can be used by host controller driver as a time base.
                            // Software writes a 1 to this bit to clear it.
                            // This is a non-EHCI status bit.
                            
    unsigned int SLI:1;         //DCSuspend – R/WC. 0=Default. 
                            // When a device controller enters a suspend state from an active state, this bit will be set to a one. The device controller
                            // clears the bit upon exiting from a suspend state.
                            // Only used by the device controller.
    unsigned int R1:1;          //Reserved. These bits are reserved and should be set to zero.
    unsigned int ULPII:1;       //ULPI Interrupt – R/WC. 0=Default.
                            // When the ULPI Viewport is present in the design, an event completion will set this interrupt.
                            // Used by both host & device controller. Only present in designs where configuration constant VUSB_HS_PHY_ULPI = 1.
    unsigned int R2:1;          //Reserved. These bits are reserved and should be set to zero.
    unsigned int HCH:1;     // HCHaIted — Read Only. 1=Default. 
                            // This bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after it has stopped
                            // executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error).
                            // Only used by the host controller.
    unsigned int RCL:1;     // Reclamation — Read Only. 0=Default. 
                            // This is a read-only status bit used to detect an empty asynchronous schedule.
                            // Only used by the host controller.
    unsigned int PS:1;          //Periodic Schedule Status — Read Only. 0=Default. 
                            // This bit reports the current real status of the Periodic Schedule. When set to zero the periodic
                            // schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic
                            // Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the
                            // same value, the Periodic Schedule is either enabled (1) or disabled (0).
                            // Only used by the host controller.
    unsigned int AS:1;          //Asynchronous Schedule Status — Read Only. 0=Default. 
                            // This bit reports the current real status of the Asynchronous Schedule. When set to zero the
                            // asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable
                            // the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the
                            // Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
                            // Only used by the host controller.
                            
    unsigned int RESERVED:16;   //Reserved. These bits are reserved and should be set to zero.
}USB_USBSTS_T;


typedef struct _USB_USBINTR{
    unsigned int UE:1;          //USB Interrupt Enable
                            // When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host/device controller will issue an
                            // interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit.