mx27_usb.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

    unsigned int PHYW:2;        // VUSB_HS_PHY16_8
    unsigned int PHYM:3;        // VUSB_HS_PHY_TYPE
    unsigned int SM:1;          // VUSB_HS_PHY_SERIAL
    unsigned int RESERVED:22;   // Reserved. These bits are reserved and should be set to zero.
} USB_HWGENERAL_T;

typedef struct _USB_HWHOST {
    unsigned int HC:1;          // VUSB_HS_HOST
    unsigned int NPORT:3;       // VUSB_HS_NUM_PORT-1
    unsigned int RESERVED:12;   // Reserved. These bits are reserved and should be set to zero.
    unsigned int TTASY:8;       // VUSB_HS_TT_ASYNC_CONTEXTS
    unsigned int TTPER:8;       // VUSB_HS_TT_PERIODIC_CONTEXTS
} USB_HWHOST_T;

typedef struct _USB_HWDEVICE {
    unsigned int DC:1;          // device capable; [VUSB_HS_DEV /= 0]
    unsigned int DEVEP:5;       // VUSB_HS_DEV_EP
    unsigned int RESERVED:26;   // Reserved. These bits are reserved and should be set to zero.
} USB_HWDEVICE_T;

typedef struct _USB_HWTXBUF {
    unsigned int TCBURST:8; // VUSB_HS_TX_BURST
    unsigned int TXADD:8;   // VUSB_HS_TX_ADD
    unsigned int TXCHANADD:8;   // VUSB_HS_TX_CHAN_ADD
    unsigned int TXLC:1;        // VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS
}USB_HWTXBUF_T;


typedef struct _USB_HWRXBUF {
    unsigned int RXBURST:8; // VUSB_HS_RX_BURST
    unsigned int RXADD:8;       // VUSB_HS_RX_ADD
    unsigned int RESERVED:16;   // Reserved. These bits are reserved and should be set to zero.
}USB_HWRXBUF_T;

typedef struct _USB_HCSPARAMS { //Port steering logic capabilities are described in this register.
    unsigned int N_PORTS:4; // Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host
                            // controller. The value of this field determines how many port registers are addressable in the Operational Register. Valid
                            // values are in the range of 1h to Fh. A zero in this field is undefined.
                            // The number of ports for a host implementation is parameterizable from 1 to 8. This field will always be 1 for
                            // device only implementation.
    unsigned int PPC:1;     // Port Power Control. This field indicates whether the host controller implementation includes port power control. A one
                            // indicates the ports have port power switches. A zero indicates the ports do not have port power switches. The value of this field
                            // affects the functionality of the Port Power field in each port status and control register.
    unsigned int RESERVED1:3;   // Reserved. These bits are reserved and should be set to zero.
    unsigned int N_PPC:4;       // Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion
                            // Controller. It is used to indicate the port routing configuration to the system software.
                            // For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention
                            // is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion
                            // controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion
                            // controller 1 and the last two are routed to companion controller 2.
                            // The number in this field must be consistent with N_PORTS and N_CC.
                            // In this implementation this field will always be "0".
    unsigned int N_CC:4;        // Number of Companion Controller (N_CC). This field indicates the number of companion controllers associated with this
                            // USB2.0 host controller.
                            // A zero in this field indicates there are no internal Companion Controllers. Port-ownership hand-off is not supported.
                            // A value larger than zero in this field indicates there are companion USB1.1 host controller(s). Port-ownership hand-offs
                            // are supported. High, Full- and Low-speed devices are supported on the host controller root ports.
                            // In this implementation this field will always be "0".
    unsigned int PI:1;          // Port Indicators (P INDICATOR). This bit indicates whether the ports support port indicator control. When set to one, the port
                            // status and control registers include a read/writeable field for controlling the state of the port indicator.
    unsigned int RESERVED2:3;   // Reserved. These bits are reserved and should be set to zero.
    unsigned int N_PTT:4;       // Number of Ports per Transaction Translator (N_PTT). This field indicates the number of ports assigned to each transaction
                            // translator within the USB2.0 host controller.
                            // For Multi-Port Host this field will always equal N_PORTS. For all other implementations, N_PTT = .0000..
                            // This in a non-EHCI field to support embedded TT.
    unsigned int N_TT:4;        // Number of Transaction Translators (N_TT). This field indicates the number of embedded transaction translators
                            // associated with the USB2.0 host controller.
                            // For Multi-Port Host this field will always equal .0001.. For all other implementions, N_TT = .0000..
    unsigned int RESERVED3:4; // Reserved. These bits are reserved and should be set to zero.
}USB_HCSPARAMS_T ;  //EHCI Compliant with extensions

typedef struct _USB_HCCPARAMS { //This register identifies multiple mode control (time-base bit functionality) addressing capability.
    unsigned int ADC:1;     // 64-bit Addressing Capability. This field will always be "0". No 64-bit addressing capability is supported.
    unsigned int PFL:1;     // Programmable Frame List Flag. If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host
                            // controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero.
                            // If set to a one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size
                            // field. The frame list must always be aligned on a 4K-page boundary. This requirement ensures that the frame list is always physically contiguous.
                            // This field will always be "1".
    unsigned int ASP:1;     //  Asynchronous Schedule Park Capability. Default = 1. If this bit is set to a one, then the host controller supports the park feature for high-speed queue
                            // heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode
                            // Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register.
                            // This field will always be "1"
    unsigned int R:1;           // Reserved. These bits are reserved and should be set to zero.
    unsigned int IST:4;     // Isochronous Scheduling Threshold. Default = implementation dependent. This field indicates, relative to the current position of the executing host
                            // controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the
                            // number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is a one, then
                            // host software assumes the host controller may cache an isochronous data structure for an entire frame.
                            // This field will always be "0".
    unsigned int EECP:8;        // EHCI Extended Capabilities Pointer. Default = 0. This optional field indicates the existence of a capabilities list. A value of 00h indicates no
                            // extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI configuration space of the first EHCI extended
                            // capability. The pointer value must be 40h or greater if implemented to maintain the consistency of the PCI header defined for this class of device.
                            // For this implementation this field is always "0".
    unsigned int RESERVED:16; // Reserved. These bits are reserved and should be set to zero.
}USB_HCCPARAMS_T ; //EHCI Compliant

typedef struct _USB_DCCPARAMS { //This register identifies multiple mode control (time-base bit functionality) addressing capability.
    unsigned int DEN:5;     // Device Endpoint Number. This field indicates the number of endpoints built into the device controller. If this controller is not device capable, then this field
                            // will be zero. Valid values are 0-16.
    unsigned int R:2;           //Reserved. These bits are reserved and should be set to zero.
    unsigned int DC:1;          // Device Capable. When this bit is 1, this controller is capable of operating as a USB 2.0 device.
    unsigned int HC:1;          //Host Capable. When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2.0 host controller.
    unsigned int RESERVED:5;    // Reserved. These bits are reserved and should be set to zero. 
} USB_DCCPARAMS_T; // Non-EHCI

typedef struct _USB_USBCMD {
    unsigned int RS:1;          //Run/Stop (RS) . Read/Write. Default 0b. 1=Run. 0=Stop.
                            // Host Controller:
                            // When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this
                            // bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC
                            // Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software
                            // should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one).
                            // Device Controller:
                            // Writing a one to this bit will cause the device controller to enable a pull-up on D+ and initiate an attach event. This control bit is not
                            // directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should
                            // use this bit to prevent an attach event before the device controller has been properly initialized. Writing a 0 to this will cause a detach event.
    unsigned int RST:1;     //Controller Reset (RESET) — Read/Write.
                            // Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset
                            // process is complete. Software cannot terminate the reset process early by writing a zero to this register.
                            // Host Controller:
                            // When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any
                            // transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a
                            // one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
                            // Device Controller:
                            // When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a
                            // one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the
                            // device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be
                            // set to 0.
    unsigned int FS:2;          //Frame List Size — (Read/Write or Read Only). Default 000b. 
                            // This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the
                            // frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD
                            //bits 15, 3 and 2.
                            // Valuesmeaning
                            // 0001024 elements (4096 bytes) Default value
                            // 001512 elements (2048 bytes)
                            // 010256 elements (1024 bytes)
                            // 011128 elements (512 bytes)
                            // 10064 elements (256 bytes)
                            // 10132 elements (128 bytes)
                            // 11016 elements (64 bytes)
                            // 1118 elements (32 bytes)
                            //Only the host controller uses this field.
    unsigned int PSE:1;     //Periodic Schedule Enable— Read/Write. Default Ob. 
                            // This bit controls whether the host controller skips processing the Periodic Schedule.