mx27_ssi.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

#define SSI_SFCSR_RFCNT0_WID		4
#define SSI_SFCSR_TFWM1_WID		4
#define SSI_SFCSR_RFWM1_WID		4
#define SSI_SFCSR_TFCNT1_WID		4
#define SSI_SFCSR_RFCNT1_WID		4

#define SSI_SOR_SYNRST_WID			1
#define SSI_SOR_WAIT_WID			2
#define SSI_SOR_INIT_WID			1
#define SSI_SOR_TX_CLR_WID			1
#define SSI_SOR_RX_CLR_WID			1
#define SSI_SOR_CLKOFF_WID			1


//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------

// SCR
#define SSI_SCR_SSIEN_DISABLE		0       // Disable SSI
#define SSI_SCR_SSIEN_ENABLE		1       // Enable SSI

#define SSI_SCR_TE_DISABLE			0       // Disable transmit section
#define SSI_SCR_TE_ENABLE			1       // Enable transmit section

#define SSI_SCR_RE_DISABLE			0       // Disable receive section
#define SSI_SCR_RE_ENABLE			1       // Enable receive section

#define SSI_SCR_NET_DISABLE		0       // Network mode not selected
#define SSI_SCR_NET_ENABLE			1       // Network mode selected

#define SSI_SCR_SYN_ASYNC			0       // Asynchronous mode selected
#define SSI_SCR_SYN_SYNC			1       // Synchronous mode selected

#define SSI_SCR_I2S_MODE_NORMAL	0       // Not in I2S mode
#define SSI_SCR_I2S_MODE_MASTER	1       // I2S master mode
#define SSI_SCR_I2S_MODE_SLAVE	2       // I2S slave mode

#define SSI_SCR_SYS_CLK_EN_OFF		0       // SYS_CLK output on SRCK port
#define SSI_SCR_SYS_CLK_EN_ON		1       // SYS_CLK output on SRCK port

#define SSI_SCR_TCH_EN_2CHAN_OFF	0       // Two channel mode disabled
#define SSI_SCR_TCH_EN_2CHAN_ON	1       // Two channel mode enabled

#define SSI_SCR_CLK_IST_HIGH		0       // Clock idle state is '1'
#define SSI_SCR_CLK_IST_LOW		1       // Clock idle state is '0'

// SISR
#define SSI_SISR_TFE0_NOT_EMPTY	0       // Transmit FIFO0 has data
#define SSI_SISR_TFE0_EMPTY		1       // Transmit FIFO0 is empty

#define SSI_SISR_TFE1_NOT_EMPTY	0       // Transmit FIFO1 has data
#define SSI_SISR_TFE1_EMPTY		1       // Transmit FIFO1 is empty

#define SSI_SISR_RFF0_NOT_FULL		0       // Space available in RX FIFO0
#define SSI_SISR_RFF0_FULL			1       // RX FIFO0 is full

#define SSI_SISR_RFF1_NOT_FULL		0       // Space available in RX FIFO1
#define SSI_SISR_RFF1_FULL			1       // RX FIFO1 is full

#define SSI_SISR_RLS_NOT_LAST_SLOT	0       // RX slot is not last in frame
#define SSI_SISR_RLS_LAST_SLOT			1       // RX slot is last in frame

#define SSI_SISR_TLS_NOT_LAST_SLOT	0       // TX slot is not last in frame
#define SSI_SISR_TLS_LAST_SLOT			1       // TX slot is last in frame

#define SSI_SISR_RFS_FS_NOT_OCCUR		0       // No RX frame sync
#define SSI_SISR_RFS_FS_OCCUR			1       // RX frame sync occurred

#define SSI_SISR_TFS_FS_NOT_OCCUR		0       // No TX frame sync
#define SSI_SISR_TFS_FS_OCCUR			1       // TX frame sync occurred

#define SSI_SISR_TUE0_NO_UNDERRUN	0       // No TX FIFO0 underrun error
#define SSI_SISR_TUE0_UNDERRUN		1       // TX FIFO0 underrun error

#define SSI_SISR_TUE1_NO_UNDERRUN	0       // No TX FIFO1 underrun error
#define SSI_SISR_TUE1_UNDERRUN		1       // TX FIFO1 underrun error

#define SSI_SISR_ROE0_NO_OVERRUN		0       // No RX FIFO0 overrun error
#define SSI_SISR_ROE0_OVERRUN			1       // RX FIFO0 overrun error

#define SSI_SISR_ROE1_NO_OVERRUN		0       // No RX FIFO1 overrun error
#define SSI_SISR_ROE1_OVERRUN			1       // RX FIFO1 overrun error

#define SSI_SISR_TDE0_NOT_READY		0       // No slot available for TX
#define SSI_SISR_TDE0_READY			1       // Empty slot available for TX

#define SSI_SISR_TDE1_NOT_READY		0       // No slot available for TX
#define SSI_SISR_TDE1_READY			1       // Empty slot available for TX

#define SSI_SISR_RDR0_NOT_READY		0       // No new data ready to read
#define SSI_SISR_RDR0_READY			1       // New data ready to read

#define SSI_SISR_RDR1_NOT_READY		0       // No new data ready to read
#define SSI_SISR_RDR1_READY			1       // New data ready to read

#define SSI_SISR_RXT_SAME				0       // No change in SATAG register
#define SSI_SISR_RXT_CHANGED			1       // SATAG register has changed

#define SSI_SISR_CMDDU_SAME			0       // No change in SACDAT register
#define SSI_SISR_CMDDU_CHANGED		1       // SACDAT register has changed

#define SSI_SISR_CMDAU_SAME			0       // No change in SACADD register
#define SSI_SISR_CMDAU_CHANGED		1       // SACADD register has changed

// SRCR
#define SSI_SRCR_REFS_EARLY			1	// Frame sync 1 bit before data
#define SSI_SRCR_REFS_NORMAL			0	 // Frame sync aligned with data

#define SSI_SRCR_RFSL_1WORD			0       // Frame sync 1 word in length
#define SSI_SRCR_RFSL_1BIT				1       // Frame sync 1 bit in length

#define SSI_SRCR_RFSI_ACTIVE_HIGH		0       // Frame sync active high
#define SSI_SRCR_RFSI_ACTIVE_LOW		1       // Frame sync active low

#define SSI_SRCR_RSCKP_RISING_EDGE	0       // Data clocked on rising edge
#define SSI_SRCR_RSCKP_FALLING_EDGE	1       // Data clocked on falling edge

#define SSI_SRCR_RSHFD_MSB_FIRST		0       // Data sent MSB first
#define SSI_SRCR_RSHFD_LSB_FIRST		1       // Data sent LSB first

#define SSI_SRCR_RXDIR_EXTERNAL		0       // RX clock is external
#define SSI_SRCR_RXDIR_INTERNAL		1       // RX clock is internal

#define SSI_SRCR_RFDIR_EXTERNAL		0       // Frame sync is external
#define SSI_SRCR_RFDIR_INTERNAL		1       // Frame sync is internal

#define SSI_SRCR_RFEN0_DISABLE			0       // RX FIFO0 disabled
#define SSI_SRCR_RFEN0_ENABLE			1       // RX FIFO0 enabled

#define SSI_SRCR_RFEN1_DISABLE			0       // RX FIFO1 disabled
#define SSI_SRCR_RFEN1_ENABLE			1       // RX FIFO1 enabled

#define SSI_SRCR_RXBIT0_MSB_ALIGNED	0       // RX data word MSB aligned
#define SSI_SRCR_RXBIT0_LSB_ALIGNED	1       // RX data word LSB aligned

#define SSI_SRCR_RXEXT_DISABLE			0       // Sign extension off
#define SSI_SRCR_RXEXT_ENABLE			1      // Sign extension on

// STCR
#define SSI_STCR_TEFS_EARLY			1       // Frame sync 1 bit before data
#define SSI_STCR_TEFS_NORMAL			0       // Frame sync aligned with data

#define SSI_STCR_TFSL_1WORD			0       // Frame sync 1 word in length
#define SSI_STCR_TFSL_1BIT				1       // Frame sync 1 bit in length

#define SSI_STCR_TFSI_ACTIVE_HIGH		0       // Frame sync active high
#define SSI_STCR_TFSI_ACTIVE_LOW		1       // Frame sync active low

#define SSI_STCR_TSCKP_RISING_EDGE	0       // Data clocked on rising edge
#define SSI_STCR_TSCKP_FALLING_EDGE	1       // Data clocked on falling edge

#define SSI_STCR_TSHFD_MSB_FIRST		0       // Data sent MSB first
#define SSI_STCR_TSHFD_LSB_FIRST		1       // Data sent LSB first

#define SSI_STCR_TXDIR_EXTERNAL		0       // TX clock is external
#define SSI_STCR_TXDIR_INTERNAL		1       // TX clock is internal

#define SSI_STCR_TFDIR_EXTERNAL		0       // Frame sync is external
#define SSI_STCR_TFDIR_INTERNAL		1       // Frame sync is internal

#define SSI_STCR_TFEN0_DISABLE			0       // TX FIFO0 disabled
#define SSI_STCR_TFEN0_ENABLE			1       // TX FIFO0 enabled

#define SSI_STCR_TFEN1_DISABLE			0       // TX FIFO1 disabled
#define SSI_STCR_TFEN1_ENABLE			1       // TX FIFO1 enabled

#define SSI_STCR_TXBIT0_MSB_ALIGNED	0       // TX data word MSB aligned
#define SSI_STCR_TXBIT0_LSB_ALIGNED	1       // TX data word LSB aligned

//SIER

#define SSI_SIER_TFEN0_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TFEN0_ENABLE			1       // TX FIFO0 enabled

#define SSI_SIER_TFEN1_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TFEN1_ENABLE			1       // TX FIFO0 enabled

#define SSI_SIER_TDE0_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TDE0_ENABLE			1       // TX FIFO0 enabled

#define SSI_SIER_TDE1_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TDE1_ENABLE			1       // TX FIFO0 enabled

#define SSI_SIER_TDMAE_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TDMAE_ENABLE			1       // TX FIFO0 enabled

#define SSI_SIER_TIE_DISABLE			0       // TX FIFO0 disabled
#define SSI_SIER_TIE_ENABLE  			1       // TX FIFO0 enabled

// STCCR
#define SSI_STCCR_WL_8BIT			0x3     // 8-bit data word
#define SSI_STCCR_WL_10BIT			0x4     // 10-bit data word
#define SSI_STCCR_WL_12BIT			0x5     // 12-bit data word
#define SSI_STCCR_WL_14BIT			0x6     // 14-bit data word
#define SSI_STCCR_WL_16BIT			0x7     // 16-bit data word
#define SSI_STCCR_WL_18BIT			0x8     // 18-bit data word
#define SSI_STCCR_WL_20BIT			0x9     // 20-bit data word
#define SSI_STCCR_WL_22BIT			0xA     // 22-bit data word
#define SSI_STCCR_WL_24BIT			0xB     // 24-bit data word

#define SSI_STCCR_PSR_DIV8_BYPASS		0       // Bypass /8 prescalar 
#define SSI_STCCR_PSR_DIV8_ENABLE		1       // Use /8 prescalar

#define SSI_STCCR_DIV2_BYPASS		0       // Bypass /2 prescalar
#define SSI_STCCR_DIV2_ENABLE		1       // Use /2 prescalar

// SRCCR
#define SSI_SRCCR_WL_8BIT			0x3     // 8-bit data word
#define SSI_SRCCR_WL_10BIT			0x4     // 10-bit data word
#define SSI_SRCCR_WL_12BIT			0x5     // 12-bit data word
#define SSI_SRCCR_WL_14BIT			0x6     // 14-bit data word
#define SSI_SRCCR_WL_16BIT			0x7     // 16-bit data word
#define SSI_SRCCR_WL_18BIT			0x8     // 18-bit data word
#define SSI_SRCCR_WL_20BIT			0x9     // 20-bit data word
#define SSI_SRCCR_WL_22BIT			0xA     // 22-bit data word
#define SSI_SRCCR_WL_24BIT			0xB     // 24-bit data word

#define SSI_SRCCR_PSR_DIV8_BYPASS		0       // Bypass /8 prescalar 
#define SSI_SRCCR_PSR_DIV8_ENABLE		1       // Use /8 prescalar

#define SSI_SRCCR_DIV2_BYPASS			0       // Bypass /2 prescalar
#define SSI_SRCCR_DIV2_ENABLE			1       // Use /2 prescalar

// SOR
#define SSI_SOR_SYNRST_NO_RESET		0       // No data reset
#define SSI_SOR_SYNRST_RESET			1       // Reset on next frame sync

#define SSI_SOR_INIT_STATE_NO_RESET	0       // No state machine reset
#define SSI_SOR_INIT_STATE_RESET		1       // Reset SSI state machine

#define SSI_SOR_TX_CLR_NO_FLUSH		0       // No flush of TX FIFOs
#define SSI_SOR_TX_CLR_FLUSH			1       // Flush TX FIFOs

#define SSI_SOR_RX_CLR_NO_FLUSH		0       // No flush of RX FIFOs
#define SSI_SOR_RX_CLR_FLUSH			1       // Flush RX FIFOs

#define SSI_SOR_CLKOFF_IPG_CLK_ON		0       // Turn on ipg_clk
#define SSI_SOR_CLKOFF_IPG_CLK_OFF	1       // Turn off ipg_clk

typedef enum {
    SSI_ID_SSI1,
    SSI_ID_SSI2,
    SSI_ID_MAX,
} SSI_ID;

// SSI error codes
typedef enum {
    SSI_ERR_NONE,
    SSI_ERR_INVALID_MODE,
    SSI_ERR_INVALID_PARM,
    SSI_ERR_IST_FAIL,
} SSI_ERR_CODE;

// SSI modes
typedef enum {
    SSI_MODE_NORMAL,
    SSI_MODE_I2SMASTER,
    SSI_MODE_I2SSLAVE,
    SSI_MODE_AC97,
    SSI_MODE_INVALID = -1,
} SSI_MODE;

// SSI channels
typedef enum {
    SSI_CHANNEL0,
    SSI_CHANNEL1,
} SSI_CHANNEL;

// SSI transfer direction
typedef enum {
    SSI_TRANSFER_TX,
    SSI_TRANSFER_RX,
} SSI_TRANSFER_DIR;

#ifdef __cplusplus
}
#endif

#endif // __MX27_SSI_H