mx27_uart.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

//-----------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004, Motorola Inc. All Rights Reserved
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT 
//
//------------------------------------------------------------------------------
//
//  Header:  mx27_uart.h
//
//  Provides definitions for UART module based on Freescale ARM9(MX27) chassis.
//
//------------------------------------------------------------------------------

#ifndef __MX27_UART_H
#define __MX27_UART_H

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------
#define UART_RXFIFO_DEPTH       32
#define UART_TXFIFO_DEPTH       32


//------------------------------------------------------------------------------
// REGISTER LAYOUT
//------------------------------------------------------------------------------
typedef struct
{
    UINT32 URXD;
    UINT32 reserved0[15];
    UINT32 UTXD;
    UINT32 reserved1[15];
    UINT32 UCR1;
    UINT32 UCR2;
    UINT32 UCR3;
    UINT32 UCR4;
    UINT32 UFCR;
    UINT32 USR1;
    UINT32 USR2;
    UINT32 UESC;
    UINT32 UTIM;
    UINT32 UBIR;
    UINT32 UBMR;
    UINT32 UBRC;
    UINT32 ONEMS;
    UINT32 UTS;
} CSP_UART_REG, *PCSP_UART_REG;

//------------------------------------------------------------------------------
// REGISTER OFFSETS
//------------------------------------------------------------------------------
#define UART_URXD_OFFSET            0x0000
#define UART_UTXD_OFFSET            0x0040
#define UART_UCR1_OFFSET            0x0080
#define UART_UCR2_OFFSET            0x0084
#define UART_UCR3_OFFSET            0x0088
#define UART_UCR4_OFFSET            0x008C
#define UART_UFCR_OFFSET            0x0090
#define UART_USR1_OFFSET            0x0094
#define UART_USR2_OFFSET            0x0098
#define UART_UESC_OFFSET            0x009C
#define UART_UTIM_OFFSET            0x00A0
#define UART_UBIR_OFFSET            0x00A4
#define UART_UBMR_OFFSET            0x00A8
#define UART_UBRC_OFFSET            0x00AC
#define UART_ONEMS_OFFSET           0x00B0
#define UART_UTS_OFFSET             0x00B4


//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define UART_URXD_RX_DATA_LSH       0
#define UART_URXD_PRERR_LSH         10
#define UART_URXD_BRK_LSH           11
#define UART_URXD_FRMERR_LSH        12
#define UART_URXD_OVRRUN_LSH        13
#define UART_URXD_ERR_LSH           14

#define UART_UTXD_TX_DATA_LSH       0

#define UART_UCR1_UARTEN_LSH        0
#define UART_UCR1_DOZE_LSH          1
#define UART_UCR1_TDMAEN_LSH        3
#define UART_UCR1_SNDBRK_LSH        4
#define UART_UCR1_RTSDEN_LSH        5
#define UART_UCR1_TXMPTYEN_LSH      6
#define UART_UCR1_IREN_LSH          7
#define UART_UCR1_RDMAEN_LSH        8
#define UART_UCR1_RRDYEN_LSH        9
#define UART_UCR1_ICD_LSH           10
#define UART_UCR1_IDEN_LSH          12
#define UART_UCR1_TRDYEN_LSH        13
#define UART_UCR1_ADBR_LSH          14
#define UART_UCR1_ADEN_LSH          15

#define UART_UCR2_SRST_LSH          0
#define UART_UCR2_RXEN_LSH          1
#define UART_UCR2_TXEN_LSH          2
#define UART_UCR2_ATEN_LSH          3
#define UART_UCR2_RTSEN_LSH         4
#define UART_UCR2_WS_LSH            5
#define UART_UCR2_STPB_LSH          6
#define UART_UCR2_PROE_LSH          7
#define UART_UCR2_PREN_LSH          8
#define UART_UCR2_RTEC_LSH          9
#define UART_UCR2_ESCEN_LSH         11
#define UART_UCR2_CTS_LSH           12
#define UART_UCR2_CTSC_LSH          13
#define UART_UCR2_IRTS_LSH          14
#define UART_UCR2_ESCI_LSH          15

#define UART_UCR3_ACIEN_LSH         0
#define UART_UCR3_INVT_LSH          1
#define UART_UCR3_RXDMUXSEL_LSH     2
#define UART_UCR3_AWAKEN_LSH        4
#define UART_UCR3_AIRINTEN_LSH      5
#define UART_UCR3_RXDSEN_LSH        6
#define UART_UCR3_ADNIMP_LSH        7
#define UART_UCR3_FRAERREN_LSH      11
#define UART_UCR3_PARERREN_LSH      12

#define UART_UCR4_DREN_LSH          0
#define UART_UCR4_OREN_LSH          1
#define UART_UCR4_BKEN_LSH          2
#define UART_UCR4_TCEN_LSH          3
#define UART_UCR4_LPBYP_LSH         4
#define UART_UCR4_IRSC_LSH          5
#define UART_UCR4_WKEN_LSH          7
#define UART_UCR4_ENIRI_LSH         8
#define UART_UCR4_INVR_LSH          9
#define UART_UCR4_CTSTL_LSH         10

#define UART_UFCR_RXTL_LSH          0
#define UART_UFCR_DCEDTE_LSH        6
#define UART_UFCR_RFDIV_LSH         7
#define UART_UFCR_TXTL_LSH          10

#define UART_USR1_AWAKE_LSH         4
#define UART_USR1_AIRINT_LSH        5
#define UART_USR1_RXDS_LSH          6
#define UART_USR1_DTRD_LSH          7
#define UART_USR1_AGTIM_LSH         8
#define UART_USR1_RRDY_LSH          9
#define UART_USR1_FRAMERR_LSH       10
#define UART_USR1_ESCF_LSH          11
#define UART_USR1_RTSD_LSH          12
#define UART_USR1_TRDY_LSH          13
#define UART_USR1_RTSS_LSH          14
#define UART_USR1_PARITYERR_LSH     15

#define UART_USR2_RDR_LSH           0
#define UART_USR2_ORE_LSH           1
#define UART_USR2_BRCD_LSH          2
#define UART_USR2_TXDC_LSH          3
#define UART_USR2_RTSF_LSH          4
#define UART_USR2_DCDIN_LSH         5
#define UART_USR2_DCDDELT_LSH       6
#define UART_USR2_WAKE_LSH          7
#define UART_USR2_IRINT_LSH         8
#define UART_USR2_RIIN_LSH          9
#define UART_USR2_RIDELT_LSH        10
#define UART_USR2_ACST_LSH          11
#define UART_USR2_IDLE_LSH          12
#define UART_USR2_DTRF_LSH          13
#define UART_USR2_TXFE_LSH          14
#define UART_USR2_ADET_LSH          15

#define UART_UESC_ESC_CHAR_LSH      0

#define UART_UTIM_TIM_LSH           0

#define UART_UBIR_INC_LSH           0

#define UART_UBMR_MOD_LSH           0

#define UART_UBRC_BCNT_LSH          0

#define UART_ONEMS_ONEMS_LSH        0

#define UART_UTS_SOFTRST_LSH        0
#define UART_UTS_RXFULL_LSH         3
#define UART_UTS_TXFULL_LSH         4
#define UART_UTS_RXEMPTY_LSH        5
#define UART_UTS_TXEMPTY_LSH        6
#define UART_UTS_RXDBG_LSH          9
#define UART_UTS_LOOPIR_LSH         10
#define UART_UTS_DBGEN_LSH          11
#define UART_UTS_LOOP_LSH           12
#define UART_UTS_FRCPERR_LSH        13


//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define UART_URXD_RX_DATA_WID       8
#define UART_URXD_PRERR_WID         1
#define UART_URXD_BRK_WID           1
#define UART_URXD_FRMERR_WID        1
#define UART_URXD_OVRRUN_WID        1
#define UART_URXD_ERR_WID           1

#define UART_UTXD_TX_DATA_WID       8

#define UART_UCR1_UARTEN_WID        1
#define UART_UCR1_DOZE_WID          1
#define UART_UCR1_TDMAEN_WID        1
#define UART_UCR1_SNDBRK_WID        1
#define UART_UCR1_RTSDEN_WID        1
#define UART_UCR1_TXMPTYEN_WID      1
#define UART_UCR1_IREN_WID          1
#define UART_UCR1_RDMAEN_WID        1
#define UART_UCR1_RRDYEN_WID        1
#define UART_UCR1_ICD_WID           2
#define UART_UCR1_IDEN_WID          1
#define UART_UCR1_TRDYEN_WID        1
#define UART_UCR1_ADBR_WID          1
#define UART_UCR1_ADEN_WID          1

#define UART_UCR2_SRST_WID          1
#define UART_UCR2_RXEN_WID          1
#define UART_UCR2_TXEN_WID          1
#define UART_UCR2_ATEN_WID          1
#define UART_UCR2_RTSEN_WID         1
#define UART_UCR2_WS_WID            1
#define UART_UCR2_STPB_WID          1
#define UART_UCR2_PROE_WID          1
#define UART_UCR2_PREN_WID          1
#define UART_UCR2_RTEC_WID          2
#define UART_UCR2_ESCEN_WID         1
#define UART_UCR2_CTS_WID           1
#define UART_UCR2_CTSC_WID          1
#define UART_UCR2_IRTS_WID          1
#define UART_UCR2_ESCI_WID          1

#define UART_UCR3_ACIEN_WID         1
#define UART_UCR3_INVT_WID          1
#define UART_UCR3_RXDMUXSEL_WID     1
#define UART_UCR3_AWAKEN_WID        1
#define UART_UCR3_AIRINTEN_WID      1
#define UART_UCR3_RXDSEN_WID        1
#define UART_UCR3_ADNIMP_WID        1
#define UART_UCR3_FRAERREN_WID      1
#define UART_UCR3_PARERREN_WID      1

#define UART_UCR4_DREN_WID          1
#define UART_UCR4_OREN_WID          1
#define UART_UCR4_BKEN_WID          1
#define UART_UCR4_TCEN_WID          1
#define UART_UCR4_LPBYP_WID         1
#define UART_UCR4_IRSC_WID          1
#define UART_UCR4_WKEN_WID          1
#define UART_UCR4_ENIRI_WID         1
#define UART_UCR4_INVR_WID          1
#define UART_UCR4_CTSTL_WID         6

#define UART_UFCR_RXTL_WID          6
#define UART_UFCR_DCEDTE_WID        1
#define UART_UFCR_RFDIV_WID         3
#define UART_UFCR_TXTL_WID          6

#define UART_USR1_AWAKE_WID         1
#define UART_USR1_AIRINT_WID        1
#define UART_USR1_RXDS_WID          1
#define UART_USR1_DTRD_WID          1
#define UART_USR1_AGTIM_WID         1
#define UART_USR1_RRDY_WID          1
#define UART_USR1_FRAMERR_WID       1
#define UART_USR1_ESCF_WID          1
#define UART_USR1_RTSD_WID          1