mx27_lcdc.h

Microsoft WinCE 6.0 BSP FINAL release source code for use with the i.MX27ADS TO2 WCE600_FINAL_MX27_S

#define LCDC_CCMR_CUR_COL_G_WID             6
#define LCDC_CCMR_CUR_COL_R_WID             6

// PCR : Panel Configuration Register
#define LCDC_PCR_PCD_WID                    6
#define LCDC_PCR_SHARP_WID                  1
#define LCDC_PCR_SCLKSEL_WID                1
#define LCDC_PCR_ACD_WID                    7
#define LCDC_PCR_ACDSEL_WID                 1
#define LCDC_PCR_REV_VS_WID                 1
#define LCDC_PCR_SWAP_SEL_WID               1
#define LCDC_PCR_END_SEL_WID                1
#define LCDC_PCR_SCLKIDLE_WID               1
#define LCDC_PCR_OEPOL_WID                  1
#define LCDC_PCR_CLKPOL_WID                 1
#define LCDC_PCR_LPPOL_WID                  1
#define LCDC_PCR_FLMPOL_WID                 1
#define LCDC_PCR_PIXPOL_WID                 1
#define LCDC_PCR_BPIX_WID                   3
#define LCDC_PCR_PBSIZ_WID                  2
#define LCDC_PCR_COLOR_WID                  1
#define LCDC_PCR_TFT_WID                    1

// HCR : Horizontal Configuration Register
#define LCDC_HCR_H_WAIT_2_WID               8
#define LCDC_HCR_H_WAIT_1_WID               8
#define LCDC_HCR_H_WIDTH_WID                6

// VCR : Vertical Configuration Register
#define LCDC_VCR_V_WAIT_2_WID               8
#define LCDC_VCR_V_WAIT_1_WID               8
#define LCDC_VCR_V_WIDTH_WID                6

// POR : Panning Offset Register
#define LCDC_POR_POR_WID                    5

// SCR : Sharp Configuration Register
#define LCDC_SCR_GRAY1_WID                  4
#define LCDC_SCR_GRAY2_WID                  4
#define LCDC_SCR_REV_TOGGLE_DELAY_WID       4
#define LCDC_SCR_CLS_RISE_DELAY_WID         8
#define LCDC_SCR_PS_RISE_DELAY_WID          6

// PCCR : PWM Contrast Control Register
#define LCDC_PCCR_PW_WID                    8
#define LCDC_PCCR_CC_EN_WID                 1
#define LCDC_PCCR_SCR_WID                   2
#define LCDC_PCCR_LDMSK_WID                 1
#define LCDC_PCCR_CLS_HI_WIDTH_WID          9

// RMCR : Refresh Mode Control Register
#define LCDC_RMCR_SELF_REF_WID              1

// DCR : DMA Control Register
#define LCDC_DCR_TM_WID                     4
#define LCDC_DCR_HM_WID                     4
#define LCDC_DCR_BURST_WID                  1

// ICR : Interrupt Configuration Register
#define LCDC_ICR_INTCON_WID                 1
#define LCDC_ICR_INTSYN_WID                 1
#define LCDC_ICR_GW_INT_CON_WID             1

// IER: Interrupt Enable Register
#define LCDC_IER_BOF_EN_WID                 1
#define LCDC_IER_EOF_EN_WID                 1
#define LCDC_IER_ERR_RES_EN_WID             1
#define LCDC_IER_UDR_ERR_EN_WID             1
#define LCDC_IER_GW_BOF_EN_WID              1
#define LCDC_IER_GW_EOF_EN_WID              1
#define LCDC_IER_GW_ERR_RES_EN_WID          1
#define LCDC_IER_GW_UDR_ERR_EN_WID          1

// ISR : Interrupt Status Register
#define LCDC_ISR_BOF_WID                    1
#define LCDC_ISR_EOF_WID                    1
#define LCDC_ISR_ERR_RES_WID                1
#define LCDC_ISR_UDR_ERR_WID                1
#define LCDC_ISR_GW_BOF_WID                 1
#define LCDC_ISR_GW_EOF_WID                 1
#define LCDC_ISR_GW_ERR_RES_WID             1
#define LCDC_ISR_GW_UDR_ERR_WID             1

// GWSAR : Graphic window Start Address Register
#define LCDC_GWSAR_GWSA_WID                 32

// GWSR : Graphic Window Size Register
#define LCDC_GWSR_GWH_WID                   10
#define LCDC_GWSR_GWW_WID                   6

// GWVPWR : Graphic Windos Virtual Page Width Register
#define LCDC_GWVPWR_GWVPW_WID               10

// GWPOR : Graphic Window Panning Offset Register
#define LCDC_GWPOR_WPOR_WID                 5

// GWPR : Graphic Window Position Register
#define LCDC_GWPR_GWYP_WID                  10
#define LCDC_GWPR_GWXP_WID                  10

// GWCR : Graphic Window Control Register
#define LCDC_GWCR_GWCKB_WID                 6
#define LCDC_GWCR_GWCKG_WID                 6
#define LCDC_GWCR_GWCKR_WID                 6
#define LCDC_GWCR_GW_RVS_WID                1
#define LCDC_GWCR_GWE_WID                   1
#define LCDC_GWCR_GWCKE_WID                 1
#define LCDC_GWCR_GWAV_WID                  8

// GWDCR : Graphic Window DMA Control Register
#define LCDC_GWDCR_GWTM_WID                 5
#define LCDC_GWDCR_GWHM_WID                 5
#define LCDC_GWDCR_GWBT_WID                 1

// AUSCR : AUS Mode Control Register
#define LCDC_AUSCR_AGWCKB_WID               8
#define LCDC_AUSCR_AGWCKG_WID               8
#define LCDC_AUSCR_AGWCKR_WID               8
#define LCDC_AUSCR_AUSMODE_WID              1

// AUSCCR : AUS Mode Cursor Control Register
#define LCDC_AUSCCR_ACUR_COL_B_WID          8
#define LCDC_AUSCCR_ACUR_COL_G_WID          8
#define LCDC_AUSCCR_ACUR_COL_R_WID          8

//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------
// SR : Size Register
#define LCDC_SR_BUSSIZE_32BIT               1   // The AHB 32Bit Width
#define LCDC_SR_BUSSIZE_64BIT               0   // The AHB 64Bit Width

// CPR : LCD Cursor Position Register
#define LCDC_CPR_OP_DISABLE                 0   // Arithmetric operation disable
#define LCDC_CPR_OP_ENABLE                  1   // Arithmetric operation enable

#define LCDC_CPR_CC_DISABLED                0   // Cursor disabled
#define LCDC_CPR_CC_OR                      1   // OR between background and cursor
#define LCDC_CPR_CC_EOR                     2   // EOR between background and cursor
#define LCDC_CPR_CC_AND                     3   // And between background and cursor

// CWHBR : LCD Cursor Width Height and Blink Register
#define LCDC_CWHBR_BK_EN_DISABLE            0   // Cursor blink disable
#define LCDC_CWHBR_BK_EN_ENABLE             1   // Cursor blink enable

#define LCDC_CWHBR_CW_CURSOR_DISABLED       0

#define LCDC_CWHBR_CH_CURSOR_DISABLED       0

#define LCDC_CWHBR_BD_MAX_DIV               255

// PCR : Panel Configuration Register
#define LCDC_PCR_SHARP_DISABLE              0   // Disable signal for Sharp HR-TFT panels.
#define LCDC_PCR_SHARP_ENABLE               1   // Enable signal for Sharp HR-TFT panels.

#define LCDC_PCR_SCLKSEL_DISABLE            0   // Disable OE and LSCLK in TFT mode when no data
#define LCDC_PCR_SCLKSEL_ENABLE             1   // Enable OE and LSCLK in TFT mode when no data

#define LCDC_PCR_ACDSEL_USE_FRM             0   // Use FRM as clock source for ACD count
#define LCDC_PCR_ACDSEL_USE_LPHSYNC         1   // Use LP/HSYN as clock source for ACD count

#define LCDC_PCR_REV_VS_NORMAL              0   // Vertical scan in normal direction
#define LCDC_PCR_REV_VS_REVERSE             1   // Vertical scan in reverse direction

#define LCDC_PCR_SWAP_SEL_16BPP             0   // Swap data for 16bpp mode
#define LCDC_PCR_SWAP_SEL_12BPP             0   // Swap data for 12bpp mode
#define LCDC_PCR_SWAP_SEL_8BPP              1   // Swap data for 8bpp mode
#define LCDC_PCR_SWAP_SEL_4BPP              1   // Swap data for 4bpp mode
#define LCDC_PCR_SWAP_SEL_2BPP              1   // Swap data for 2bpp mode
#define LCDC_PCR_SWAP_SEL_1BPP              1   // Swap data for 1bpp mode

#define LCDC_PCR_END_SEL_LITTLE_ENDIAN      0   // Image download into memory as little endian format
#define LCDC_PCR_END_SEL_BIG_ENDIAN         1   // Image download into memory as big endian format

#define LCDC_PCR_SCLKIDLE_DISABLE           0   // Disable LSCLK when VSYNC idle
#define LCDC_PCR_SCLKIDLE_ENABLE            1   // Enable LSCLK when VSYNC idle

#define LCDC_PCR_OEPOL_ACTIVE_HIGH          0   // Output polarity active high
#define LCDC_PCR_OEPOL_ACTIVE_LOW           1   // Output polarity active low

#define LCDC_PCR_CLKPOL_NEG_EDGE            0   // Active negative edge of LSCLK
#define LCDC_PCR_CLKPOL_POS_EDGE            1   // Active positive edge of LSCLK

#define LCDC_PCR_LPPOL_ACTIVE_HIGH          0   // Active high
#define LCDC_PCR_LPPOL_ACTIVE_LOW           1   // Active low

#define LCDC_PCR_FLMPOL_ACTIVE_HIGH         0   // Active high
#define LCDC_PCR_FLMPOL_ACTIVE_LOW          1   // Active low

#define LCDC_PCR_PIXPOL_ACTIVE_HIGH         0   // Active high
#define LCDC_PCR_PIXPOL_ACTIVE_LOW          1   // Active low

// Note: 
// To set normal 18bpp mode:
//  BPIX = 110
//  END_SEL = 0
//  SWAP_SEL = X (don抰 care)
// To set Microsoft PAL_BGR 18bpp mode:
//  BPIX = 110
//  END_SEL = 1
//  SWAP_SEL = 1
#define LCDC_PCR_BPIX_1BPP                  0   // 1bpp
#define LCDC_PCR_BPIX_2BPP                  1   // 2bpp
#define LCDC_PCR_BPIX_4BPP                  2   // 4bpp
#define LCDC_PCR_BPIX_8BPP                  3   // 8bpp
#define LCDC_PCR_BPIX_12BPP                 4   // 12bpp
#define LCDC_PCR_BPIX_16BPP                 5   // 16bpp
#define LCDC_PCR_BPIX_18BPP                 6   // 18bpp

#define LCDC_PCR_PBSIZ_1BIT                 0   //  1 bit panel bus width
#define LCDC_PCR_PBSIZ_4BIT                 2   //  4 bit panel bus width
#define LCDC_PCR_PBSIZ_8BIT                 3   //  8 bit panel bus width

#define LCDC_PCR_COLOR_MONOCHROME           0   // Monochrome LCD panel
#define LCDC_PCR_COLOR_COLOR                1   // Color LCD panel

#define LCDC_PCR_TFT_PASSIVE                0   // Passive display
#define LCDC_PCR_TFT_ACTIVE                 1   // Active display

// PCCR : PWM Contrast Control Register
#define LCDC_PCCR_PW_MAX                    255 // PWM max

#define LCDC_PCCR_CC_EN_DISABLE             0   // Contrast control off
#define LCDC_PCCR_CC_EN_ENABLE              1   // Contrast control on

#define LCDC_PCCR_SCR_LINEPULSE             0   // Clock source to PWM counter is line pulse
#define LCDC_PCCR_SCR_PIXELCLK              1   // Clock source to PWM counter is pixel clock
#define LCDC_PCCR_SCR_LCDCLK                2   // Clock source to PWM counter is LCD clock

#define LCDC_PCCR_LDMSK_DISABLE             0   // LD[15:0] is always normal
#define LCDC_PCCR_LDMSK_ENABLE              1   // LD[15:0] is always 0

// RMCR : Refresh Mode Control Register
#define LCDC_RMCR_SELF_REF_DISABLE          0   // Self refresh disable
#define LCDC_RMCR_SELF_REF_ENABLE           1   // Self refresh enable

// DCR : DMA Control Register
#define LCDC_DCR_BURST_DYNAMIC              0   // Burst length is dynamic
#define LCDC_DCR_BURST_FIXED                1   // Burst length is fixed

// ICR : Interrupt Configuration Register
#define LCDC_ICR_INTCON_EOF                 0   // Interrupt flag is set when EOF reached
#define LCDC_ICR_INTCON_BOF                 1   // Interrupt flag is set when BOF reached

#define LCDC_ICR_INTSYN_MEMORY              0   // Interrupt flag is set on loading last/first frame data from memory
#define LCDC_ICR_INTSYN_PANEL               1   // Interrupt flag is set on loading last/first frame data to LCD panel

#define LCDC_ICR_GW_INT_CON_END             0   // Interrupt flag is set when end of graphic window is reached
#define LCDC_ICR_GW_INT_CON_BEG             1   // Interrupt flag is set when beginning of graphic window is reached

// IER: Interrupt Enable Register
#define LCDC_IER_BOF_EN_DISABLE             0   // BOF interrupt disable
#define LCDC_IER_BOF_EN_ENABLE              1   // BOF interrupt enable

#define LCDC_IER_EOF_EN_DISABLE             0   // EOF interrupt disable
#define LCDC_IER_EOF_EN_ENABLE              1   // EOF interrupt enable

#define LCDC_IER_ERR_RES_DISABLE            0   // Error reponse interrupt disable
#define LCDC_IER_ERR_RES_ENABLE             1   // Error reponse interrupt enable

#define LCDC_IER_UDR_ERR_EN_DISABLE         0   // Underrun error reponse interrupt disable
#define LCDC_IER_UDR_ERR_EN_ENABLE          1   // Underrun error reponse interrupt enable

#define LCDC_IER_GW_BOF_EN_DISABLE          0   // Graphic window BOF interrupt disable
#define LCDC_IER_GW_BOF_EN_ENABLE           1   // Graphic window BOF interrupt enable

#define LCDC_IER_GW_EOF_EN_DISABLE          0   // Graphic window EOF interrupt disable
#define LCDC_IER_GW_EOF_EN_ENABLE           1   // Graphic window EOF interrupt enable

#define LCDC_IER_GW_ERR_RES_EN_DISABLE      0   // Graphic window error reponse interrupt disable
#define LCDC_IER_GW_ERR_RES_EN_ENABLE       1   // Graphic window error reponse interrupt enable

#define LCDC_IER_GW_UDR_ERR_EN_DISABLE      0   // Graphic window underrun error reponse interrupt disable
#define LCDC_IER_GW_UDR_ERR_EN_ENABLE       1   // Graphic window underrun error reponse interrupt enable

// ISR : Interrupt Status Register
#define LCDC_ISR_BOF_NO_INTERRUPT           0   // No BOF interrupt
#define LCDC_ISR_BOF_INTERRUPT              1   // BOF interrupt

#define LCDC_ISR_EOF_NO_INTERRUPT           0   // No EOF interrupt
#define LCDC_ISR_EOF_INTERRUPT              1   // EOF interrupt

#define LCDC_ISR_ERR_RES_DISABLE            0   // No error reponse interrupt
#define LCDC_ISR_ERR_RES_ENABLE             1   // Error reponse interrupt

#define LCDC_ISR_UDR_ERR_NO_INTERRUPT       0   // No underrun error reponse interrupt
#define LCDC_ISR_UDR_ERR_INTERRUPT          1   // Underrun error reponse interrupt

#define LCDC_ISR_GW_BOF_NO_INTERRUPT        0   // No graphic window BOF interrupt
#define LCDC_ISR_GW_BOF_INTERRUPT           1   // Graphic window BOF interrupt

#define LCDC_ISR_GW_EOF_NO_INTERRUPT        0   // No graphic window EOF interrupt
#define LCDC_ISR_GW_EOF_INTERRUPT           1   // Graphic window EOF interrupt

#define LCDC_ISR_GW_ERR_RES_NO_INTERRUPT    0   // No graphic window error reponse interrupt
#define LCDC_ISR_GW_ERR_RES_INTERRUPT       1   // Graphic window error reponse interrupt

#define LCDC_ISR_GW_UDR_ERR_NO_INTERRUPT    0   // No graphic window underrun error reponse interrupt
#define LCDC_ISR_GW_UDR_ERR_INTERRUPT       1   // Graphic window underrun error reponse interrupt

// GWCR : Graphic Window Control Register
#define LCDC_GWCR_GW_RVS_NORMAL             0   // Vertical scan in normal direction
#define LCDC_GWCR_GW_RVS_REVERSE            1   // Vertical scan in reverse direction

#define LCDC_GWCR_GWE_DISABLE               0   // Graphic window disable
#define LCDC_GWCR_GWE_ENABLE                1   // Graphic window enable

#define LCDC_GWCR_GWCKE_DISABLE             0   // Graphic window color keying disable
#define LCDC_GWCR_GWCKE_ENABLE              1   // Graphic window color keying enable

#define LCDC_GWCR_GWAV_TRANSPARENT          0   // Graphic window totally transparent
#define LCDC_GWCR_GWAV_OPAQUE               1   // Graphic window totally opaque

// GWDCR : Graphic Window DMA Control Register
#define LCDC_GWDCR_GWBT_DYNAMIC             0   // Burst length is dynamic
#define LCDC_GWDCR_GWBT_FIXED               1   // Burst length is fixed

// AUSCR : AUS Mode Control Register
#define LCDC_AUSCR_AUSMODE_NORMAL           0   // Normal Mode 
#define LCDC_AUSCR_AUSMODE_AUS              1   // AUS Mode

// mode
#ifndef DISPLAY_MODE_SHPQVGA
#define DISPLAY_MODE_SHPQVGA    0
#endif
#ifndef DISPLAY_MODE_NECVGA
#define DISPLAY_MODE_NECVGA     1
#endif
#ifndef DISPLAY_MODE_NTSC
#define DISPLAY_MODE_NTSC       2
#endif
#ifndef DISPLAY_MODE_PAL
#define DISPLAY_MODE_PAL        3
#endif
#ifndef DISPLAY_MODE_NONE
#define DISPLAY_MODE_NONE       4
#endif


#ifdef __cplusplus
}
#endif

#endif // __MX27_LCDC_H