mod764.inc

周立功公司开发的单片机手册

; Include file for 87LPC764 SFR Definitions for Asm
; Philips Semiconductors. Revision 1.0, 04/20/99

AUXR1   data    0A2h    ; Auxiliary Function Register

CMP1    data    0ACh    ; Comparator 1 Control Register
CMP2    data    0ADh    ; Comparator 2 Control Register
DIVM    data    095h    ; CPU Clock Divide-By-M Control

I2CFG   data    0C8h    ; I2C Configuration Register
CT0     bit     I2CFG.0 ; Clock Time Select 0
CT1     bit     I2CFG.1 ; Clock Time Select 1
TIRUN   bit     I2CFG.4 ; Timer I Run Enable
CLRTI   bit     I2CFG.5 ; Clear Timer I
MASTRQ  bit     I2CFG.6 ; Master Request
SLAVEN  bit     I2CFG.7 ; Slave Enable
I2CON   data    0D8h    ; I2C Control Register
MASTER  bit     I2CON.1 ; Master Status
STP     bit     I2CON.2 ; Stop Detect Flag
STR     bit     I2CON.3 ; Start Detect Flag
ARL     bit     I2CON.4 ; Arbitration Loss Flag
DRDY    bit     I2CON.5 ; Data Ready Flag
ATN     bit     I2CON.6 ; Attention: I2C Interrupt Flag
RDAT    bit     I2CON.7 ; I2C Read Data
I2DAT   data    0D9h    ; I2C Data Register
IEN0    data    0A8h    ; Interrupt Enable Register 0

EBO     bit     IEN0.5  ; Brownout Interrupt Enable
EWD     bit     IEN0.6  ; Watchdog Interrupt Enable

IEN1    data    0E8h    ; Interrupt Enable Register 1
EI2     bit     IEN1.0  ; I2C Interrupt Enable
EKB     bit     IEN1.1  ; Keyboard Interrupt Enable
EC2     bit     IEN1.2  ; Comparator 2 Interrupt Enable
EC1     bit     IEN1.5  ; Comparator 1 Interrupt Enable
ETI     bit     IEN1.7  ; Timer I Interrupt Enable
IP0     data    0B8h    ; Interrupt Priority 0 Low Byte

PBO     bit     IP0.5   ; Brownout Interrupt Priority
PWD     bit     IP0.6   ; Watchdog Interrupt Priority
IP0H    data    0B7h    ; Interrupt Priority 0 High Byte
IP1     data    0F8h    ; Interrupt Priority 1 Low Byte
PI2     bit     IP1.0   ; I2C Interrupt Priority
PKB     bit     IP1.1   ; Keyboard Interrupt Priority
PC2     bit     IP1.2   ; Comparator 2 Interrupt Priority
PC1     bit     IP1.5   ; Comparator 1 Interrupt Priority
PTI     bit     IP1.7   ; Timer I Interrupt Priority
IP1H    data    0F7h    ; Interrupt Priority 1 High Byte
KBI     data    086h    ; Keyboard Interrupt

CMP2O   bit     P0.0    ; P0, bit 0 is also the Comparator 2 Output
CIN2B   bit     P0.1    ; P0, bit 1 is also the Comparator Input B
CIN2A   bit     P0.2    ; P0, bit 2 is also the Comparator Input A
CIN1B   bit     P0.3    ; P0, bit 3 is also the Comparator Input B
CIN1A   bit     P0.4    ; P0, bit 4 is also the Comparator Input A
CMPREF  bit     P0.5    ; P0, bit 5 is also the Comparator Reference Input
CMP1O   bit     P0.6    ; P0, bit 6 is also the Comparator 1 Output
Input/Toggle Output
P0M1    data    084h    ; P0 Mode Register 1
P0M2    data    085h    ; P0 Mode Register 2
Output

SCL     bit     P1.2    ; P1, bit 2 is also the I2C Bus Clock Line
SDA     bit     P1.3    ; P1, bit 3 is also the I2C Bus Data Line

RST     bit     P1.5    ; P1, bit 5 is also the Reset Pin
; P1.6 and P1.7 have no alternate function
P1M1    data    091h    ; P1 Mode Register 1
P1M2    data    092h    ; P1 Mode Register 2

X2      bit     P2.0    ; P2, bit 0 is also the X2 Pin
CLKOUT  bit     P2.0    ; P2, bit 0 is also the CLKOUT Pin
X1      bit     P2.1    ; P2, bit 1 is also the X1 Pin
P2M1    data    0A4h    ; P2 Mode Register 1
P2M2    data    0A5h    ; P2 Mode Register 2

F1      bit     PSW.1   ; Flag 1

PT0AD   data    0F6h    ; Port 0 digital Input Disable

SADDR   data    0A9h    ; Serial Port Address
SADEN   data    0B9h    ; Serial Port Address Enable

WDCON   data    0A7h    ; Watchdog Control Register
WDRST   data    0A6h    ; Watchdog Reset (Feed) Register