📄 ad9958.c
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/**********************************************
AD9958.C file
The AD9985's Operation file
Creat by Computer-lov Date: 2005.8.30
Last edit date:2005.8.30
Copyright(C) 2005-2015 Computer-lov
All rights reserved
************************************************/
#include "AD9958.H"
#include <ADUC841.h>
//hardware connection
//#define PWR_DWN_CTL P2_0
#define MASTER_RESET P0_0
#define SDIO_3 P2_7
#define SDIO_2 P2_6
#define SDIO_1 P2_5
#define SDIO_0 P2_4
#define SCLK P0_1
#define CS P0_2
void delay(void)
{
unsigned int i;
for(i=0;i<10;i++);
}
void run(void)
{
//unsigned int i;
IO_UPDATA=0;
IO_UPDATA=0;
IO_UPDATA=0;
IO_UPDATA=0;
IO_UPDATA=0;
IO_UPDATA=0;
//for(i=0;i<200;i++);
IO_UPDATA=0;
IO_UPDATA=1;
// for(i=0;i<200;i++);
}
void write_a_byte(unsigned char w_data)
{
unsigned char i;
for(i=0;i<8;i++)
{
SDIO_0=(w_data & 0x80);
w_data<<=1;
SCLK=1;
// delay();
SCLK=0;
}
}
void write_CSR(unsigned char w_data)
{
SDIO_3=0;
CS=0;
write_a_byte(0x00); //write address 0. CSR's address is 0.
write_a_byte(w_data);
CS=1;
SDIO_3=1;
}
void write_FR1(unsigned char w_data1,unsigned char w_data2,unsigned char w_data3)
{
SDIO_3=0;
delay();
CS=0;
write_a_byte(0x01); //write address 1. FR1's address is 0x01
write_a_byte(w_data1);
write_a_byte(w_data2);
write_a_byte(w_data3);
CS=1;
SDIO_3=1;
}
void write_FR2(unsigned char w_data1,unsigned char w_data2)
{
SDIO_3=0;
CS=0;
write_a_byte(0x02); //write address 2
write_a_byte(w_data1);
write_a_byte(w_data2);
CS=1;
SDIO_3=1;
}
void write_CFR(unsigned char w_data1,unsigned char w_data2,unsigned char w_data3)
{
SDIO_3=0;
CS=0;
write_a_byte(0x03);
write_a_byte(w_data1);
write_a_byte(w_data2);
write_a_byte(w_data3);
CS=1;
SDIO_3=1;
}
void write_CTW0(unsigned long int F_word) //Channel Frequency Tuning Word (CTW0)
{
SDIO_3=0;
CS=0;
write_a_byte(0x04);
write_a_byte(((unsigned char *)(&F_word))[0]);
write_a_byte(((unsigned char *)(&F_word))[1]);
write_a_byte(((unsigned char *)(&F_word))[2]);
write_a_byte(((unsigned char *)(&F_word))[3]);
CS=1;
SDIO_3=1;
}
void write_CPW0(unsigned int P_word) //Channel Phase1 Offset Word (CPW0) (0x05)
{
SDIO_3=0;
CS=0;
write_a_byte(0x05);
write_a_byte(((unsigned char *)(&P_word))[0]);
write_a_byte((((unsigned char *)(&P_word))[1])&0x3F);
CS=1;
SDIO_3=1;
}
void write_ACR(unsigned long int A_word)
{
SDIO_3=0;
CS=0;
write_a_byte(0x06);
write_a_byte(((unsigned char *)(&A_word))[1]);
write_a_byte(((unsigned char *)(&A_word))[2]);
write_a_byte(((unsigned char *)(&A_word))[3]);
CS=1;
SDIO_3=1;
}
void write_LSR(unsigned char rising,unsigned char falling)
{
SDIO_3=0;
CS=0;
write_a_byte(0x07);
write_a_byte(rising);
write_a_byte(falling);
CS=1;
SDIO_3=1;
}
void write_RDW(unsigned long rising)
{
SDIO_3=0;
CS=0;
write_a_byte(0x08);
write_a_byte(((unsigned char *)(&rising))[0]);
write_a_byte(((unsigned char *)(&rising))[1]);
write_a_byte(((unsigned char *)(&rising))[2]);
write_a_byte(((unsigned char *)(&rising))[3]);
CS=1;
SDIO_3=1;
}
void write_FDW(unsigned long falling)
{
SDIO_3=0;
CS=0;
write_a_byte(0x09);
write_a_byte(((unsigned char *)(&falling))[0]);
write_a_byte(((unsigned char *)(&falling))[1]);
write_a_byte(((unsigned char *)(&falling))[2]);
write_a_byte(((unsigned char *)(&falling))[3]);
CS=1;
SDIO_3=1;
}
void write_CTWn(unsigned char n,unsigned long int w_data)
{
SDIO_3=0;
CS=0;
write_a_byte(n+0x09); //CTWn's address is n+0x09.n>=1 and n<=15.
write_a_byte(((unsigned char *)(&w_data))[0]);
write_a_byte(((unsigned char *)(&w_data))[1]);
write_a_byte(((unsigned char *)(&w_data))[2]);
write_a_byte(((unsigned char *)(&w_data))[3]);
CS=1;
SDIO_3=1;
}
#define PLL_DIV 5
#define systemp_frequency (22.1184*1000000*PLL_DIV)
void set_frequency(unsigned long int f)
{
unsigned long int temp;
temp=(unsigned long int)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);
write_CTW0(temp);
}
unsigned long int change(unsigned long int f)
{
unsigned long int temp;
temp=(unsigned long int)f*(0xFFFFFFFF/(float)systemp_frequency+1.0/systemp_frequency);
return temp;
}
void AD9958_init(void)
{
unsigned int i;
// PWR_DWN_CTL=0;
MASTER_RESET=0;
for(i=0;i<10000;i++);
CS=1;
SCLK=0;
SDIO_3=1;
MASTER_RESET=1;
for(i=0;i<10000;i++);
MASTER_RESET=0;
for(i=0;i<100;i++);
delay();
write_CSR(0xF0); //70
write_FR1(0x14,0x50,0x00);
write_FR2(0x00,0x00);
write_CFR(0x00,0x03,0x00); //no modulation
// write_CFR(0xc0,0x03,0x00); //auto sweep,AM
// write_CTW0(0x7ff00000);
//set_frequency(10000000);
write_CPW0(0x00);
// write_ACR(0x00);
// write_ACR(0xFF03FF);
write_LSR(0xFF,0xFF);
write_RDW(0x0ff00000);
write_FDW(0x0ff00000);
write_CTWn(1,0x7E000000);
// modulated signal
write_CSR(0x70); //70
set_frequency(1000);
write_ACR(0xff13af); //0x3af 100% modulation
//调幅载波
write_CSR(0x80);
write_ACR(0xff10ff);
set_frequency(10000000);
run();
}
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