📄 new 2.h
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#define P4IN_ 0x001C /* Port 4 Input */
const sfrb P4IN = P4IN_;
#define P4OUT_ 0x001D /* Port 4 Output */
sfrb P4OUT = P4OUT_;
#define P4DIR_ 0x001E /* Port 4 Direction */
sfrb P4DIR = P4DIR_;
#define P4SEL_ 0x001F /* Port 4 Selection */
sfrb P4SEL = P4SEL_;
/************************************************************
* DIGITAL I/O Port5/6
************************************************************/
#define P5IN_ 0x0030 /* Port 5 Input */
const sfrb P5IN = P5IN_;
#define P5OUT_ 0x0031 /* Port 5 Output */
sfrb P5OUT = P5OUT_;
#define P5DIR_ 0x0032 /* Port 5 Direction */
sfrb P5DIR = P5DIR_;
#define P5SEL_ 0x0033 /* Port 5 Selection */
sfrb P5SEL = P5SEL_;
#define P6IN_ 0x0034 /* Port 6 Input */
const sfrb P6IN = P6IN_;
#define P6OUT_ 0x0035 /* Port 6 Output */
sfrb P6OUT = P6OUT_;
#define P6DIR_ 0x0036 /* Port 6 Direction */
sfrb P6DIR = P6DIR_;
#define P6SEL_ 0x0037 /* Port 6 Selection */
sfrb P6SEL = P6SEL_;
/************************************************************
* USART
************************************************************/
#define PENA 0x80 /* UCTL */
#define PEV 0x40
#define SPB 0x20 /* to distinguish from stackpointer SP */
#define CHAR 0x10
#define LISTEN 0x08
#define SYNC 0x04
#define MM 0x02
#define SWRST 0x01
#define CKPH 0x80 /* UTCTL */
#define CKPL 0x40
#define SSEL1 0x20
#define SSEL0 0x10
#define URXSE 0x08
#define TXWAKE 0x04
#define STC 0x02
#define TXEPT 0x01
#define FE 0x80 /* URCTL */
#define PE 0x40
#define OE 0x20
#define BRK 0x10
#define URXEIE 0x08
#define URXWIE 0x04
#define RXWAKE 0x02
#define RXERR 0x01
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ 0x0070 /* UART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ 0x0072 /* UART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb U0BR0 = U0BR0_;
#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb U0BR1 = U0BR1_;
#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */
const sfrb U0RXBUF = U0RXBUF_;
#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */
sfrb U0TXBUF = U0TXBUF_;
/* Alternate register names */
#define UCTL0_ 0x0070 /* UART 0 Control */
sfrb UCTL0 = UCTL0_;
#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL0 = UTCTL0_;
#define URCTL0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL0 = URCTL0_;
#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL0 = UMCTL0_;
#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR00 = UBR00_;
#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR10 = UBR10_;
#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF0 = RXBUF0_;
#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF0 = TXBUF0_;
#define UCTL_0_ 0x0070 /* UART 0 Control */
sfrb UCTL_0 = UCTL_0_;
#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */
sfrb UTCTL_0 = UTCTL_0_;
#define URCTL_0_ 0x0072 /* UART 0 Receive Control */
sfrb URCTL_0 = URCTL_0_;
#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */
sfrb UMCTL_0 = UMCTL_0_;
#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */
sfrb UBR0_0 = UBR0_0_;
#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */
sfrb UBR1_0 = UBR1_0_;
#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */
const sfrb RXBUF_0 = RXBUF_0_;
#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer */
sfrb TXBUF_0 = TXBUF_0_;
/************************************************************
* USART 1
************************************************************/
#define U1CTL_ 0x0078 /* UART 1 Control */
sfrb U1CTL = U1CTL_;
#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */
sfrb U1TCTL = U1TCTL_;
#define U1RCTL_ 0x007A /* UART 1 Receive Control */
sfrb U1RCTL = U1RCTL_;
#define U1MCTL_ 0x007B /* UART 1 Modulation Control */
sfrb U1MCTL = U1MCTL_;
#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */
sfrb U1BR0 = U1BR0_;
#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb U1BR1 = U1BR1_;
#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */
const sfrb U1RXBUF = U1RXBUF_;
#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */
sfrb U1TXBUF = U1TXBUF_;
#define UCTL1_ 0x0078 /* UART 1 Control */
sfrb UCTL1 = UCTL1_;
#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL1 = UTCTL1_;
#define URCTL1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL1 = URCTL1_;
#define UMCTL1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL1 = UMCTL1_;
#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR01 = UBR01_;
#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR11 = UBR11_;
#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF1 = RXBUF1_;
#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF1 = TXBUF1_;
#define UCTL_1_ 0x0078 /* UART 1 Control */
sfrb UCTL_1 = UCTL_1_;
#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */
sfrb UTCTL_1 = UTCTL_1_;
#define URCTL_1_ 0x007A /* UART 1 Receive Control */
sfrb URCTL_1 = URCTL_1_;
#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */
sfrb UMCTL_1 = UMCTL_1_;
#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */
sfrb UBR0_1 = UBR0_1_;
#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */
sfrb UBR1_1 = UBR1_1_;
#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */
const sfrb RXBUF_1 = RXBUF_1_;
#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */
sfrb TXBUF_1 = TXBUF_1_;
/************************************************************
* Timer A
************************************************************/
#define TAIV_ 0x012E /* Timer A Interrupt Vector Word */
sfrw TAIV = TAIV_;
#define TACTL_ 0x0160 /* Timer A Control */
sfrw TACTL = TACTL_;
#define TACCTL0_ 0x0162 /* Timer A Capture/Compare Control 0 */
sfrw TACCTL0 = TACCTL0_;
#define TACCTL1_ 0x0164 /* Timer A Capture/Compare Control 1 */
sfrw TACCTL1 = TACCTL1_;
#define TACCTL2_ 0x0166 /* Timer A Capture/Compare Control 2 */
sfrw TACCTL2 = TACCTL2_;
#define TAR_ 0x0170 /* Timer A */
sfrw TAR = TAR_;
#define TACCR0_ 0x0172 /* Timer A Capture/Compare 0 */
sfrw TACCR0 = TACCR0_;
#define TACCR1_ 0x0174 /* Timer A Capture/Compare 1 */
sfrw TACCR1 = TACCR1_;
#define TACCR2_ 0x0176 /* Timer A Capture/Compare 2 */
sfrw TACCR2 = TACCR2_;
/* Alternate register names */
#define CCTL0_ 0x0162 /* Timer A Capture/Compare Control 0 */
sfrw CCTL0 = CCTL0_;
#define CCTL1_ 0x0164 /* Timer A Capture/Compare Control 1 */
sfrw CCTL1 = CCTL1_;
#define CCTL2_ 0x0166 /* Timer A Capture/Compare Control 2 */
sfrw CCTL2 = CCTL2_;
#define CCR0_ 0x0172 /* Timer A Capture/Compare 0 */
sfrw CCR0 = CCR0_;
#define CCR1_ 0x0174 /* Timer A Capture/Compare 1 */
sfrw CCR1 = CCR1_;
#define CCR2_ 0x0176 /* Timer A Capture/Compare 2 */
sfrw CCR2 = CCR2_;
#define TASSEL2 0x0400 /* unused */ /* to distinguish from UART SSELx */
#define TASSEL1 0x0200 /* Timer A clock source select 0 */
#define TASSEL0 0x0100 /* Timer A clock source select 1 */
#define ID1 0x0080 /* Timer A clock input devider 1 */
#define ID0 0x0040 /* Timer A clock input devider 0 */
#define MC1 0x0020 /* Timer A mode control 1 */
#define MC0 0x0010 /* Timer A mode control 0 */
#define TACLR 0x0004 /* Timer A counter clear */
#define TAIE 0x0002 /* Timer A counter interrupt enable */
#define TAIFG 0x0001 /* Timer A counter interrupt flag */
#define MC_0 00*0x10 /* Timer A mode control: 0 - Stop */
#define MC_1 01*0x10 /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 02*0x10 /* Timer A mode control: 2 - Continous up */
#define MC_3 03*0x10 /* Timer A mode control: 3 - Up/Down */
#define ID_0 00*0x40 /* Timer A input divider: 0 - /1 */
#define ID_1 01*0x40 /* Timer A input divider: 1 - /2 */
#define ID_2 02*0x40 /* Timer A input divider: 2 - /4 */
#define ID_3 03*0x40 /* Timer A input divider: 3 - /8 */
#define TASSEL_0 00*0x100 /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 01*0x100 /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 02*0x100 /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 03*0x100 /* Timer A clock source select: 3 - INCLK */
#define CM1 0x8000 /* Capture mode 1 */
#define CM0 0x4000 /* Capture mode 0 */
#define CCIS1 0x2000 /* Capture input select 1 */
#define CCIS0 0x1000 /* Capture input select 0 */
#define SCS 0x0800 /* Capture sychronize */
#define SCCI 0x0400 /* Latched capture signal (read) */
#define CAP 0x0100 /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 0x0080 /* Output mode 2 */
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