📄 sd.h
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#ifndef __PC5000_SD_H
#define __PC5000_SD_H
//#include <bsp.h>
#include <nkintr.h>
#include <bulverde.h>
//#include"eboot_debug.h"
#include<windows.h>
#include <nkintr.h>
//#include <GPIO.h>
#include <ethdbg.h>
#include "halether.h"
#include <nkintr.h>
#include <pehdr.h>
#include <romldr.h>
//#include "ethdown.h"
//#include "xllp_defs.h"
//#include "xllp_ethernet.h"
//#include "sd.h"
//#include "xllp_pwm.h"
#include <pcireg.h>
//#include"xllp_mmc.h"
//#include"xllp_dmac.h"
#define MMC_RXFIFO_SIZE 32
#define MMC_TXFIFO_SIZE 32
// GPIO definitions for the MMC controller
#define MMCCLK_PIN GPIO_32;
#define MMCCMD_PIN GPIO_112;
#define MMCDAT0_PIN GPIO_92;
#define MMCDAT1_PIN GPIO_109;
#define MMCDAT2_PIN GPIO_110;
#define MMCDAT3_PIN GPIO_111;
#define GPIO6_MMCCLK_PIN GPIO_6
#define GPIO8_MMCCS0_PIN GPIO_8
#define GPIO10_DAT0_PIN_POLL GPIO_10
#define GPIO12_DAT1_PIN_INTERRUPT GPIO_12
// GPIO control register offsets
#define GPIO_GPLR0 0x0000 // pin level register
#define GPIO_GRER0 0x0030 // Rising Edge Detect register
#define GPIO_GFER0 0x003C // Falling Edge Detect register
#define GPIO_GPSR0 0x0018 // pin output select register
#define GPIO_GPDR0 0x000C // pin direction register
#define GPIO_GAFR0_L 0x00054 // alternate function register
#define GPIO_ALT_FN_CLEAR_BITS 0x03
#define GPIO_ALT_FN_1_BITS 0x01
#define GPIO_6_ALTFN_SHIFT 12
#define GPIO_8_ALTFN_SHIFT 16
#define GPIO_10_ALTFN_SHIFT 20
#define GPIO_12_ALTFN_SHIFT 24
// MMC Controller register offsets
#define MMC1_STRPCL 0x0000 // clock start/stop
#define MMC1_STAT 0x0004 // MMC Status register
#define MMC1_CLKRT 0x0008 // clock rate
#define MMC1_SPI 0x000C // SPI mode control
#define MMC1_CMDAT 0x0010 // command/response/data sequence
#define MMC1_RESTO 0x0014 // response timeout
#define MMC1_RDTO 0x0018 // expected data read timeout
#define MMC1_BLKLEN 0x001C // data phase block length
#define MMC1_NOB 0x0020 // number of blocks
#define MMC1_PRTBUF 0x0024 // partial MMC TX Fifo
#define MMC1_IMASK 0x0028 // interrupt mask
#define MMC1_IREG 0x002C // interrupt register
#define MMC1_CMD 0x0030 // command
#define MMC1_ARGH 0x0034 // MSW of command argument
#define MMC1_ARGL 0x0038 // LSW of command argument
#define MMC1_RES 0x003C // response Fifo
// OS Timer register offsets
#define OST_COUNT_REG 0x0010 // OS Timer count register
// bit definitions for MMC_STRPCL
#define MMC_STRPCL_START_CLOCK 0x02
#define MMC_STRPCL_STOP_CLOCK 0x01
// bit definitions for MMC_IMASK
#define MMC_IMASK_DATA_TRAN_DONE_INT_MASKED (1 << 0)
#define MMC_IMASK_PROG_DONE_INT_MASKED (1 << 1)
#define MMC_IMASK_END_CMD_INT_MASKED (1 << 2)
#define MMC_IMASK_STOP_CMD_INT_MASKED (1 << 3)
#define MMC_IMASK_CLOCK_OFF_INT_MASKED (1 << 4)
#define MMC_IMASK_RXFIFO_REQ_INT_MASKED (1 << 5)
#define MMC_IMASK_TXFIFO_REQ_INT_MASKED (1 << 6)
#define MMC_IMASK_TRANSMIT_TIMEOUT_INT_MASKED (1 << 7)
#define MMC_IMASK_DATA_ERROR_INT_MASKED (1 << 8)
#define MMC_IMASK_RESPONSE_ERROR_INT_MASKED (1 << 9)
#define MMC_IMASK_STALLED_READ_INT_MASKED (1 << 10)
#define MMC_IMASK_SDIO_INT_MASKED (1 << 11)
#define MMC_IMASK_SDIO_SUSPEND_ACK_INT_MASKED (1 << 12)
#define MMC_IMASK_ALL_INTERRUPTS_MASKED (MMC_IMASK_DATA_TRAN_DONE_INT_MASKED | \
MMC_IMASK_PROG_DONE_INT_MASKED | \
MMC_IMASK_END_CMD_INT_MASKED | \
MMC_IMASK_STOP_CMD_INT_MASKED | \
MMC_IMASK_CLOCK_OFF_INT_MASKED | \
MMC_IMASK_RXFIFO_REQ_INT_MASKED | \
MMC_IMASK_TXFIFO_REQ_INT_MASKED) | \
MMC_IMASK_TRANSMIT_TIMEOUT_INT_MASKED | \
MMC_IMASK_DATA_ERROR_INT_MASKED | \
MMC_IMASK_RESPONSE_ERROR_INT_MASKED | \
MMC_IMASK_STALLED_READ_INT_MASKED | \
MMC_IMASK_SDIO_INT_MASKED | \
MMC_IMASK_SDIO_SUSPEND_ACK_INT_MASKED
// bit definitions for MMC_IREG
#define MMC_IREG_DATA_TRAN_DONE (1 << 0)
#define MMC_IREG_PROG_DONE (1 << 1)
#define MMC_IREG_END_CMD (1 << 2)
#define MMC_IREG_STOP_CMD (1 << 3)
#define MMC_IREG_CLOCK_IS_OFF (1 << 4)
#define MMC_IREG_RXFIFO_REQ (1 << 5)
#define MMC_IREG_TXFIFO_REQ (1 << 6)
#define MMC_IREG_TINT (1 << 7)
#define MMC_IREG_DAT_ERR (1 << 8)
#define MMC_IREG_RES_ERR (1 << 9)
#define MMC_IREG_RD_STALLED (1 << 10)
#define MMC_IREG_SDIO_INT (1 << 11)
#define MMC_IREG_SDIO_SUSPEND_ACK (1 << 12)
#define MMC_IREG_INTERRUPTS 0x1FFF
// bit definitions for MMC_CMDAT
#define MMC_CMDAT_RESPONSE_NONE 0x00 // no response
#define MMC_CMDAT_RESPONSE_R1 0x01 // expected R1 response
#define MMC_CMDAT_RESPONSE_R2 0x02 // expected R2 response
#define MMC_CMDAT_RESPONSE_R3 0x03 // expected R3 response
#define MMC_CMDAT_DATA_EN (1 << 2) // data transfer to follow
#define MMC_CMDAT_DATA_WRITE (1 << 3) // data transfer is a write
#define MMC_CMDAT_STREAM (1 << 4) // data transfer is stream mode
#define MMC_CMDAT_EXPECT_BUSY (1 << 5) // the command uses busy signalling
#define MMC_CMDAT_INIT (1 << 6) // add init clocks
#define MMC_CMDAT_DMA_ENABLE (1 << 7) // enable DMA
#define MMC_CMDAT_SD_4DAT (1 << 8) // enable 4 bit data transfers
#define MMC_CMDAT_STOP_TRAN (1 << 10) // stop data transmission
#define MMC_CMDAT_SDIO_INT_EN (1 << 11) // enable controller to check for an SDIO interrupt from the card
#define MMC_CMDAT_SDIO_SUSPEND (1 << 12) // SDIO CMD 52, suspend current data transfer
#define MMC_CMDAT_SDIO_RESUME (1 << 13) // SDIO CMD 52, resume a suspended data transfer
// bit definitions for MMC_STAT
#define MMC_STAT_READ_TIMEOUT (1 << 0)
#define MMC_STAT_RESPONSE_TIMEOUT (1 << 1)
#define MMC_STAT_WRITE_DATA_CRC_ERROR (1 << 2)
#define MMC_STAT_READ_DATA_CRC_ERROR (1 << 3)
#define MMC_STAT_SPI_READ_TOKEN_ERROR (1 << 4)
#define MMC_STAT_RESPONSE_CRC_ERROR (1 << 5)
#define MMC_STAT_CLOCK_ENABLED (1 << 8)
#define MMC_STAT_FLASH_ERROR (1 << 9)
#define MMC_STAT_SPI_WR_ERROR (1 << 10)
#define MMC_STAT_DATA_TRANSFER_DONE (1 << 11)
#define MMC_STAT_PROGRAM_DONE (1 << 12)
#define MMC_STAT_END_CMD_RES (1 << 13)
#define MMC_STAT_RD_STALLED (1 << 14)
#define MMC_STAT_SDIO_INT (1 << 15)
#define MMC_STAT_SDIO_SUSPEND_ACK (1 << 16)
// bit definition for MMC_PRTBUF
#define MMC_PRTBUF_BUFFER_PARTIAL_FULL (1 << 0)
typedef enum {
Idle = -1 ,
CommandSend = 1,
CommandComplete = 2,
ResponseWait = 3,
WriteDataTransfer = 4,
WriteDataTransferDone = 5,
ProgramWait = 6,
WriteDataDone = 7,
ReadDataTransfer = 8,
ReadDataTransferDone = 9,
ReadDataDone = 10,
} SDHSTATE;
// PXA27x hardware specific context
#define SDH_INTERRUPT_ZONE SDCARD_ZONE_0
#define SDH_SEND_ZONE SDCARD_ZONE_1
#define SDH_RESPONSE_ZONE SDCARD_ZONE_2
#define SDH_RECEIVE_ZONE SDCARD_ZONE_3
#define SDH_CLOCK_ZONE SDCARD_ZONE_4
#define SDH_TRANSMIT_ZONE SDCARD_ZONE_5
#define SDH_SDBUS_INTERACTION_ZONE SDCARD_ZONE_7
#define SDH_INTERRUPT_ZONE_ON ZONE_ENABLE_0
#define SDH_SEND_ZONE_ON ZONE_ENABLE_1
#define SDH_RESPONSE_ZONE_ON ZONE_ENABLE_2
#define SDH_RECEIVE_ZONE_ON ZONE_ENABLE_3
#define SDH_CLOCK_ZONE_ON ZONE_ENABLE_4
#define SDH_TRANSMIT_ZONE_ON ZONE_ENABLE_5
#define SDH_SDBUS_INTERACTION_ZONE_ON ZONE_ENABLE_7
#define SDH_CARD_CONTROLLER_PRIORITY 100
#define SDH_DEFAULT_RESPONSE_TIMEOUT_CLOCKS 64
#define SDH_DEFAULT_DATA_TIMEOUT_CLOCKS 0xFFFF
#define SDH_RESPONSE_FIFO_DEPTH 8 //
#define SDH_MAX_BLOCK_SIZE 1023
#define SDH_MIN_BLOCK_SIZE 32
extern void msWait(unsigned );
extern void Wait(unsigned );
#define SD_DEFAULT_CARD_ID_CLOCK_RATE 100000 // 100 khz
#endif⌨️ 快捷键说明
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