uart232_top.ucf

spi接口的vhdl实现

NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_reset0/snk_ff_clk_rst_gen/reset_out_i"    MAXDELAY = 11 ns;
NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_reset0/snk_ff_clk_rst_gen/fifo_reset_out_i" MAXDELAY = 11 ns;
NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_reset0/rdclk0_rst_gen/fifo_reset_out_i" MAXDELAY = 11 ns;
NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_reset0/rdclk0_rst_gen/reset_out_i" MAXDELAY = 11 ns;
############### END DO NOT EDIT ###########################

############################################################################ 
# Place Timing Ignores on all static configuration signals 
# If these are driven statically from a register, than apply to TIG 
# attributes to them to create proper timing ignore paths. If these 
# are driven statically from a wrapper file, then the TIG is not needed. 
############################################################################ 
#NET "SnkAFThresAssert(*)"  TIG; 
#NET "SnkAFThresNegate(*)"  TIG; 
#NET "FifoAFMode(*)"        TIG; 
#NET "NumDip4Errors(*)"     TIG; 
#NET "NumTrainSequences(*)" TIG; 
#NET "RSClkPhase"           TIG; 
#NET "RSClkDiv"             TIG; 


###############################################################################
# Source Side constraints 
# The following set the constraints for the source core pl4_lite_src_top.edf. 
# If the Sink and Source back-end files are looped backing using 
# pl4_fifo_loopback, then the back-end clocks should not be set here. 
###############################################################################

######################################################################
# Constrain the DCMs and associated BUFGMUXes
# NOTE: This section may require modification depending on
#       the clocking of the user's logic.
######################################################################
 
INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_clk0/tdclk_dcm0"  LOC = DCM_X1Y0;
INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_clk0/tdclk_bufg0" LOC = BUFGMUX_X1Y1;

# Set the frequency of the PL4 Source side 
NET "SysClk_P" TNM_NET = "SysClk_P"; 
TIMESPEC "TS_SysClk_P" = PERIOD "SysClk_P" 90 MHz HIGH 50 % INPUT_JITTER 200 ps; 

NET "uart232_pl4_lite_src_top0/TSClk_GP" TNM_NET = "TSClk_GP";
TIMESPEC "TS_TSClk_GP" = PERIOD "TSClk_GP" 23  MHz HIGH 50% ;

# The following are only required if the back-end clocking is not
# otherwise set
#NET "SrcFFClk" TNM_NET = "SrcFFClk"; 
#TIMESPEC "TS_SrcFFClk" = PERIOD "SrcFFClk" 90 MHz HIGH 50.00%; 

#NET "SrcCalClk" TNM_NET = "SrcCalClk"; 
#TIMESPEC "TS_SrcCalClk" = PERIOD "SrcCalClk" 23 MHz HIGH 50.00%; 

#NET "SrcStatClk" TNM_NET = "SrcStatClk"; 
#TIMESPEC "TS_SrcStatClk" = PERIOD "SrcStatClk" 23 MHz HIGH 50.00%; 

###############################################################################
# Source Area Constraint and Pinout 
# The following constraints are pertaining to the footprint of source block.
# Footprint details: 
# IO aligned from the bottom of bank 9. (west side) 
###############################################################################

###############################################################################
# Area constraint, blockRAM placement, Source IO banking 
# Note that the area group must encompass all Source pins. 
###############################################################################

 
INST "SysClk*" LOC = "Bank2";
#INST "TDClk*" LOC = "Bank2";
#INST "TCtl*" LOC = "Bank2";
#INST "TDat*" LOC = "Bank2";

# Constraint path from TStat to IOB Register (LVDS)
NET "TStat_P(0)" OFFSET = IN 0ns BEFORE "TSClk_P";
NET "TStat_P(1)" OFFSET = IN 0ns BEFORE "TSClk_P";
NET "TStat_N(0)" OFFSET = IN 0ns BEFORE "TSClk_N";
NET "TStat_N(1)" OFFSET = IN 0ns BEFORE "TSClk_N";

NET "TStat_P(0)"  NODELAY; 
NET "TStat_P(1)"  NODELAY; 
NET "TStat_N(0)"  NODELAY; 
NET "TStat_N(1)"  NODELAY; 

# Source Area Group
INST uart232_pl4_lite_src_top0/* AREA_GROUP = AG_pl4_lite_src ; 
AREA_GROUP "AG_pl4_lite_src" RANGE = SLICE_X0Y0:SLICE_X45Y59; 

# FIFO BlockRAM locations 
#INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_core0/pl4_lite_src_fifo0/PL4_Source_FIFO/pl4_async_burst_fifo_ram0/BlockRAM360" LOC = "RAMB16_X0Y2";
#INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_core0/pl4_lite_src_fifo0/PL4_Source_FIFO/pl4_async_burst_fifo_ram0/BlockRAM361" LOC = "RAMB16_X0Y3";

# Calendar Logic BlockRAM locations 
#INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" LOC = "RAMB16_X0Y6";

################################################################################
#$RCSfile: src_cal_ucf.ejava,v $
#$Revision: 1.1.4.1 $
#$Date: 2007/03/16 10:42:36 $


######################################################################
# Initialize the calendar logic
# Sample initialization values are shown below, defaulting the calendar 
# to a round-robin sequence.
######################################################################
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_00 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_01 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_02 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_03 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_04 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_05 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_06 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_07 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_08 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_09 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0A = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0B = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0C = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0D = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0E = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/cram/BlockRam" INIT_0F = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100; 
 

#EOF: $RCSfile $ 

##########################################################
# Source Core I/O and Reset Constraints
##########################################################
################# DO NOT EDIT ############################
INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat0_ff" IOB=TRUE;
INST "uart232_pl4_lite_src_top0/U0/pl4_lite_src_cal0/tstat1_ff" IOB=TRUE;

NET "uart232_pl4_lite_src_top0/U0/pl4_lite_src_reset0/src_tsclk_reset/reset_out_i"     MAXDELAY = 11 ns;
NET "uart232_pl4_lite_src_top0/U0/pl4_lite_src_reset0/src_ff_clk_rst/reset_out_i"      MAXDELAY = 11 ns;
NET "uart232_pl4_lite_src_top0/U0/pl4_lite_src_reset0/src_ff_clk_rst/fifo_reset_out_i" MAXDELAY = 11 ns;
NET "uart232_pl4_lite_src_top0/U0/pl4_lite_src_reset0/src_clk_rst/reset_out_i"         MAXDELAY = 11 ns;
NET "uart232_pl4_lite_src_top0/U0/pl4_lite_src_reset0/src_clk_rst/fifo_reset_out_i"    MAXDELAY = 11 ns;
############### END DO NOT EDIT ###########################

######################################################################
# Place Timing Ignores on all static configuration signals
# If these are driven statically from a register, than apply to TIG
# attributes to them to create proper timing ignore paths. If these
# are driven statically from a wrapper file, then the TIG is not needed.
######################################################################
#NET "SrcAFThresAssert(*)" TIG;
#NET "SrcAFThresNegate(*)" TIG;
#NET "DataMaxT(*)"         TIG;
#NET "AlphaData(*)"        TIG;
#NET "SrcBurstLen(*)"      TIG;
#NET "NumDip2Errors(*)"    TIG;
#NET "NumDip2Matches(*)"   TIG;