uart232_top.ucf

spi接口的vhdl实现

################################################################################
# File:                  pl4_lite_wrapper.ucf
# Date:                  13 July 2006
# Target Device:         3s1200e-fg400-4
################################################################################
# Description:
# This UCF file is provided as an example constraint file for the SPI-4.2 core.
# This file can be modified to target other device and package configurations.
# For details on how to retarget the core, see the User Guide.   
################################################################################

CONFIG PART = 3s1200e-fg400-4;

	
###############################################################################
# Sink Side constraints 
# The following set the constraints for the sink core pl4_lite_snk_top.edf. 
# If the Sink and Source back-end files are looped backing using 
# pl4_lite_fifo_loopback, then the back-end clocks should not be set here. 
###############################################################################

######################################################################
# Constrain the DCMs and associated BUFGMUXes
# NOTE: This section may require modification depending on
#       the clocking of the user's logic.
######################################################################
 
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_clk0/rdclk_dcm0"  LOC = DCM_X1Y3;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_clk0/rdclk_bufg0" LOC = BUFGMUX_X1Y11;

######################################################################
# RDClk DCM Phase Shift
# The PHASE SHIFT of the RDCLK can be modified to change the alignment 
# of the RDClk relative to the RDat & RCtl inputs.
# Note: The instance name may require modification to reflect the 
# user's design hierarchy and synthesis tools.
######################################################################
 
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_clk0/rdclk_dcm0" CLKOUT_PHASE_SHIFT = FIXED;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_clk0/rdclk_dcm0" PHASE_SHIFT = 62;

###############################################################################
# PL4 FIFO Loopback constraints 
# The following set the constraints for back-end design. This assumes 
# that the wrapper file is used to loopback the Sink data to the Source 
# side. If this is not true, then the following should be commented 
# out, and instead, use the constraints listed under Sink Side 
# Constraints. 
###############################################################################

NET "CalClk" TNM_NET = "CalClk"; 
TIMESPEC "TS_CalClk" = PERIOD "CalClk" 23 MHz HIGH 50 %; 

NET "LoopbackClk" TNM_NET = "LoopbackClk"; 
TIMESPEC "TS_LoopbackClk" = PERIOD "LoopbackClk" 90 MHz HIGH 50 % ; 

# Set the frequency of the PL4 Sink side 
NET "RDClk_P" TNM_NET = "RDClk_P"; 
TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 90 MHz HIGH 50 % INPUT_JITTER 200 ps;

NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/EnRSClk_int*" TNM = FFS snk_cal_flops;
TIMESPEC "TS_SnkCalFlops" = FROM "snk_cal_flops" TO "snk_cal_flops" "TS_RDClk_P"/ 4;

# The following are only required if the back-end clocking is not
# otherwise set
#NET "SnkFFClk" TNM_NET = "SnkFFClk"; 
#TIMESPEC "TS_SnkFFClk" = PERIOD "SnkFFClk" 90 MHz HIGH 50.00%; 

#NET "SnkCalClk" TNM_NET = "SnkCalClk"; 
#TIMESPEC "TS_SnkCalClk" = PERIOD "SnkCalClk" 23 MHz HIGH 50.00%; 

#NET "SnkStatClk" TNM_NET = "SnkStatClk"; 
#TIMESPEC "TS_SnkStatClk" = PERIOD "SnkStatClk" 23 MHz HIGH 50.00%;


###############################################################################
# Sink Area Constraint and IO Banking 
# The following constraints are pertaining to the footprint of the sink core.
###############################################################################

###############################################################################
# Area constraint, blockRAM placement, Sink IO banking
# Note that the area group must encompass all Sink pins. 
###############################################################################
INST uart232_pl4_lite_snk_top0/* AREA_GROUP = AG_pl4_lite_snk ;
AREA_GROUP "AG_pl4_lite_snk" RANGE = SLICE_X0Y119:SLICE_X45Y60;


# FIFO BlockRAM locations 
#INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_afifo0/pl4_generic_fifo0/generic_fifo_ram0/BlockRAM360" LOC = "RAMB16_X0Y10";
#INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_afifo0/pl4_generic_fifo0/generic_fifo_ram0/BlockRAM361" LOC = "RAMB16_X0Y11";

# Calendar Logic BlockRAM location
#INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" LOC =  "RAMB16_X0Y13";

# IO
NET "RCtl*" NODELAY;
NET "RDat*" NODELAY;

#INST "RCtl*" LOC = "Bank0";
#INST "RDat*" LOC = "Bank0";
INST "RDClk*" LOC = "Bank0";  
###############################################################################
# Sink Side DDR I/O Timing Constraints
###############################################################################
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rdat_clk0*" TNM = RD_DDR_R;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rdat_clk180*" TNM = RD_DDR_F;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rctl_clk0*" TNM = RC_DDR_R;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_io0/rctl_clk180*" TNM = RC_DDR_F;

OFFSET = IN -1.11 ns VALID 3.33 ns BEFORE RDClk_P TIMEGRP RD_DDR_R ;
OFFSET = IN -6.66 ns VALID 3.33 ns BEFORE RDClk_P TIMEGRP RD_DDR_F ;
OFFSET = IN -1.11 ns VALID 3.33 ns BEFORE RDClk_P TIMEGRP RC_DDR_R ;
OFFSET = IN -6.66 ns VALID 3.33 ns BEFORE RDClk_P TIMEGRP RC_DDR_F ;


################################################################################
#$RCSfile: snk_cal_ucf.ejava,v $
#$Revision: 1.1.4.1 $
#$Date: 2007/03/16 10:42:36 $


######################################################################
# Initialize the calendar logic
# Sample initialization values are shown below, defaulting the calendar 
# to a round-robin sequence.
######################################################################
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_00 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_01 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_02 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_03 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_04 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_05 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_06 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_07 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_08 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_09 = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0A = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0B = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0C = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0D = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0E = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
# INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/CalRAM/BlockRam" INIT_0F = 0F0E0D0C0B0A090807060504030201000F0E0D0C0B0A09080706050403020100;
 

#EOF: $RCSfile $ 
##########################################################
# Sink Core I/O and Reset Constraints
##########################################################
################# DO NOT EDIT ############################
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rsclk_ff"     IOB=TRUE;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rstat0_ff"    IOB=TRUE;
INST "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rstat1_ff"    IOB=TRUE;

NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/rsclk_rst"        MAXDELAY = 11 ns;
NET "uart232_pl4_lite_snk_top0/U0/pl4_lite_snk_reset0/snk_stat_clk_rst_gen/reset_out_i"  MAXDELAY = 11 ns;