pl4_lite_fifo_loopback_write.v

spi接口的vhdl实现

//****************************************************************************
// PL4 FIFO Loopback Verilog RTL Design
//****************************************************************************
//                                                                       
// This file is owned and controlled by Xilinx and must be used solely   
// for design, simulation, implementation and creation of design files   
// limited to Xilinx devices or technologies. Use with non*Xilinx        
// devices or technologies is expressly prohibited and immediately       
// terminates your license.                                              
//                                                                       
// Xilinx products are not intended for use in life support              
// appliances, devices, or systems. Use in such applications is          
// expressly prohibited.                                                 
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_fifo_loopback_write.v
//*****************************************************************************
// Structure: pl4_lite_fifo_loopback_write.v
//*****************************************************************************
// Description:  This code implements the write module for the synthesizable
// FIFO loopback for the PL4 Core.  It contains a bank of registers for the
// data that is being looped back to the Source FIFO and a State Machine to
// control when data is read into and written out of the module/
//*****************************************************************************

`timescale 1ps/1ps

//****************************************************************************
// Module Declaration
//****************************************************************************
module pl4_lite_fifo_loopback_write(
  //**************************************************************************
  // Common Signals
  //**************************************************************************
  Reset_n,
  LoopbackClk,
  LoopbackEn_n,
  RReq,
  RAck,

  //**************************************************************************
  // PL4 Sink Signals
  //**************************************************************************
  Data,
  Addr,
  Mods,
  SOP,
  EOP,
  Err,

  //**************************************************************************
  // PL4 Source Signals
  //**************************************************************************
  SrcFFData,
  SrcFFAddr,
  SrcFFMod,
  SrcFFSOP,
  SrcFFEOP,
  SrcFFErr,
  SrcFFAlmostFull_n,
  SrcFFWrEn_n
  );

  input         Reset_n;
  input         LoopbackClk;    
  input         LoopbackEn_n; 
  output        RReq;
  input         RAck;
  input [31:0] Data;
  input   [1:0] Mods;
  input   [7:0] Addr;
  input         SOP;
  input         EOP;
  input         Err;
  output [31:0] SrcFFData;
  output   [1:0] SrcFFMod;
  output  [7:0] SrcFFAddr;
  output        SrcFFSOP;
  output        SrcFFEOP;
  output        SrcFFErr;
  input         SrcFFAlmostFull_n;
  output        SrcFFWrEn_n;


  wire          Reset_n;
  wire          LoopbackClk;
  wire          LoopbackEn_n;
  reg           RReq;
  wire          RAck;
  wire [31:0]  Data;
  wire   [1:0]  Mods;
  wire  [7:0]   Addr;
  wire          SOP;
  wire          EOP;
  wire          Err;
  reg  [31:0]  SrcFFData;
  reg   [1:0]   SrcFFMod;
  reg   [7:0]   SrcFFAddr;
  reg           SrcFFSOP;
  reg           SrcFFEOP;
  reg           SrcFFErr;
  wire          SrcFFAlmostFull_n;
  reg           SrcFFWrEn_n;

  //**************************************************************************
  // Parameter Declarations
  //**************************************************************************
  parameter TFF = 1000;

  //**************************************************************************
  // State Machine Variable and Type Declarations
  // StateType:
  //
  //    IDLE             : Reset and IDLE state.
  //    TRANSFER         : A data transfer request. This indicates that the
  //                       loopback is enabled and the Source FIFO can
  //                       accept data. Remain in this state until the
  //                       loopback is disabled, or the Source FIFO is
  //                       almost full.
  //
  // Variables:
  //    State      - holds current state of state machine
  //**************************************************************************
  parameter IDLE     = 2'b01;
  parameter TRANSFER = 2'b10;
  reg [1:0] State;

  always @ (posedge LoopbackClk or negedge Reset_n)
  begin:gen_main_reg 
    if (!Reset_n)
      begin
        SrcFFData   <= #TFF 32'h0000;
        SrcFFMod    <= #TFF 2'b00;
        SrcFFAddr   <= #TFF 8'h00;
        SrcFFSOP    <= #TFF 1'b0;
        SrcFFEOP    <= #TFF 1'b0;
        SrcFFErr    <= #TFF 1'b0;
        SrcFFWrEn_n <= #TFF 1'b1;
      end
    else
      begin
        SrcFFData   <= #TFF Data;
        SrcFFAddr   <= #TFF Addr;            
        SrcFFMod    <= #TFF Mods;
        SrcFFSOP    <= #TFF SOP;
        SrcFFEOP    <= #TFF EOP;
        SrcFFErr    <= #TFF Err;
        SrcFFWrEn_n <= #TFF !RAck;
        end
  end

  //**************************************************************************
  // State Machine Process
  //**************************************************************************
  always @ (negedge Reset_n or posedge LoopbackClk)
  begin:state_machine
    if (!Reset_n)
      begin
        State <= #TFF IDLE;
        RReq  <= #TFF 1'b0;
      end
    else

      case (State)
        //********************************************************************
        // IDLE
        //********************************************************************
        IDLE:
          if (SrcFFAlmostFull_n & !LoopbackEn_n)
            begin
              State <= #TFF TRANSFER;
              RReq  <= #TFF 1'b1;
            end
          else
            begin
              State <= #TFF IDLE;
              RReq  <= #TFF 1'b0;
            end

        //********************************************************************
        // TRANSFER
        //********************************************************************
        TRANSFER:
          if (!SrcFFAlmostFull_n | LoopbackEn_n)
            begin
              State <= #TFF IDLE;
              RReq  <= #TFF 1'b0;
            end
          else
            begin
              State <= #TFF TRANSFER;
              RReq  <= #TFF 1'b1;
            end

        //********************************************************************
        // Error and Default States
        //********************************************************************
        default:
          begin
            State <= #TFF IDLE;
            RReq  <= #TFF 1'b0;
          end
      endcase
  end

endmodule