uart232_pl4_lite_snk_top.v

spi接口的vhdl实现

//****************************************************************************
// PL4 Sink Verilog Module 
//****************************************************************************
//                                                                       
// This file is owned and controlled by Xilinx and must be used solely   
// for design, simulation, implementation and creation of design files   
// limited to Xilinx devices or technologies. Use with non*Xilinx        
// devices or technologies is expressly prohibited and immediately       
// terminates your license.                                              
//                                                                       
// Xilinx products are not intended for use in life support              
// appliances, devices, or systems. Use in such applications is          
// expressly prohibited.                                                 
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_snk_top.v
//
// Description:  Module declaration for the Sink Core
//
//*****************************************************************************

`timescale 1ps/1ps

//******************************************************************************
// PL4 Sink Module Declaration
//******************************************************************************
module uart232_pl4_lite_snk_top (
  // common signals
  reset_n,
  snkfiforeset_n,

   dcmreset_rdclk,
  locked_rdclk,
  dcmlost_rdclk,
  snkclksrdy,

  // sink general purpose clocks
  rdclk180_gp,
  rdclk0_gp,
 
  // Sink Calendar I/O
  snkcalendar_m,
  snkcalendar_len,
  snkcalclk,
  snkcalwren_n,
  snkcaladdr,
  snkcaldata,
  snkcaldataout,
  snkstatclk,
  snkstat,
  snkstataddr,
  snkstatwr_n,
  snkstatmask,		    

  // FIFO I/O
  snkffclk,
  snkffrden_n,
  snkffaddr,
  snkffdata,
  snkffmod,
  snkffsop,
  snkffeop,
  snkffbursterr,
  snkfferr,
  snkffdip4err,
  snkffpayloaddip4,
  snkffpayloaderr,
  snkffvalid,
  snkffempty_n,
  snkffalmostempty_n,
  snkalmostfull_n,
  snkoverflow_n,

  // Control and status signals
  snken,
  snkoof,
  snkbuserr,
  snkbuserrstat,
  snktrainvalid,
  snkdip2errrequest,

  // FIFO status interface
  rsclk,
  rstat,

  // PL4 sink bus
   rdclk_p,
  rdclk_n,
   rdat_p,
  rdat_n,
  rctl_p,
  rctl_n,

  // Configuration signals
  snkafthresassert,
  snkafthresnegate,
  fifoafmode,
  numdip4errors,
  numtrainsequences,
  rsclkphase,
  rsclkdiv
  ) /* synthesis syn_black_box */ ;

  //****************************************************************************
  // I/O declarations
  //****************************************************************************
  input         reset_n;
  input         snkfiforeset_n;

   input         dcmreset_rdclk;
  output        dcmlost_rdclk;
  output        locked_rdclk;
  output        snkclksrdy;

  output        rdclk180_gp;
  output        rdclk0_gp;
 
  input   [7:0] snkcalendar_m;
  input   [8:0] snkcalendar_len;
  input         snkcalclk;
  input         snkcalwren_n;
  input   [8:0] snkcaladdr;
  input   [7:0] snkcaldata;
  output  [7:0] snkcaldataout;
  input         snkstatclk;
  input  [31:0] snkstat;
  input  [3:0] 	snkstataddr;
  input 	snkstatwr_n;
  input  [15:0] snkstatmask;
  input         snkffclk;
  input         snkffrden_n;
  output  [7:0] snkffaddr;
  output [31:0] snkffdata;
  output  [1:0] snkffmod;
  output        snkffsop;
  output        snkffeop;
  output        snkffbursterr;
  output        snkfferr;
  output        snkffdip4err;
  output        snkffpayloaddip4;
  output        snkffpayloaderr;
  output        snkffvalid;
  output        snkffempty_n;
  output        snkffalmostempty_n;
  output        snkalmostfull_n;
  output        snkoverflow_n;
  input         snken;
  output        snkoof;
  output        snkbuserr;
  output  [7:0] snkbuserrstat;
  output        snktrainvalid;
  input         snkdip2errrequest;
  output        rsclk;
  output  [1:0] rstat;
   input         rdclk_p  /* synthesis .ispad=1 */ ;
  input         rdclk_n  /* synthesis .ispad=1 */ ;
   input  [15:0] rdat_p   /* synthesis .ispad=1 */ ;
  input  [15:0] rdat_n   /* synthesis .ispad=1 */ ;
  input         rctl_p   /* synthesis .ispad=1 */ ;
  input         rctl_n   /* synthesis .ispad=1 */ ;
  input   [8:0] snkafthresassert;
  input   [8:0] snkafthresnegate;
  input   [1:0] fifoafmode;
  input   [3:0] numdip4errors;
  input   [3:0] numtrainsequences;
  input         rsclkphase;
  input         rsclkdiv;

endmodule //pl4_lite_snk_top