pl4_lite_fifo_loopback.v

spi接口的vhdl实现

//****************************************************************************
// PL4 FIFO Loopback Verilog RTL Design
//****************************************************************************
//                                                                       
// This file is owned and controlled by Xilinx and must be used solely   
// for design, simulation, implementation and creation of design files   
// limited to Xilinx devices or technologies. Use with non*Xilinx        
// devices or technologies is expressly prohibited and immediately       
// terminates your license.                                              
//                                                                       
// Xilinx products are not intended for use in life support              
// appliances, devices, or systems. Use in such applications is          
// expressly prohibited.                                                 
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_fifo_loopback.v
//*****************************************************************************
// Structure: 
//              pl4_lite_fifo_loopback.v
//                 |
//                 +  pl4_lite_fifo_loopback_write.v
//                 |
//                 +  pl4_lite_fifo_loopback_read.v
//*****************************************************************************
// Description:  This code implements a synthesizable FIFO loopback for the
// PL4 Core.  This code connects the Loopback Read and Write Mdules together.
//*****************************************************************************

`timescale 1ps/1ps

//*****************************************************************************
// Module Declaration
//*****************************************************************************
module pl4_lite_fifo_loopback(
  //***************************************************************************
  // Common Signals
  //***************************************************************************
  Reset_n,
  LoopbackClk,
  StatLoopbackClk,

  LoopbackEn_n,

  //***************************************************************************
  // PL4 Sink Signals
  //***************************************************************************
  SnkFFData,
  SnkFFAddr,
  SnkFFMod,
  SnkFFSOP,
  SnkFFEOP,
  SnkFFErr,
  SnkFFAlmostEmpty_n,
  SnkFFEmpty_n,
  SnkFFValid,
  SnkFFRdEn_n,

  //***************************************************************************
  // PL4 Source Signals
  //***************************************************************************
  SrcFFData,
  SrcFFAddr,
  SrcFFMod,
  SrcFFSOP,
  SrcFFEOP,
  SrcFFErr,
  SrcFFAlmostFull_n,
  SrcFFWrEn_n,

  //***************************************************************************
  // PL4 Status Signals
  //***************************************************************************
  SrcStat,
  SrcStatAddr,
  SrcStatCh,
  SrcStatChValid,  

  SnkStat,
  SnkStatAddr,
  SnkStatWr_n,
  SnkStatMask

  );

  input         Reset_n;
  input         LoopbackClk;
  input         StatLoopbackClk;
  input         LoopbackEn_n;
  input [31:0] SnkFFData;
  input   [1:0] SnkFFMod;
  input   [7:0] SnkFFAddr;
  input         SnkFFSOP;
  input         SnkFFEOP;
  input         SnkFFErr;
  input         SnkFFAlmostEmpty_n;
  input         SnkFFEmpty_n;
  input         SnkFFValid;
  output        SnkFFRdEn_n;
  output [31:0] SrcFFData;
  output   [1:0] SrcFFMod;
  output  [7:0] SrcFFAddr;
  output        SrcFFSOP;
  output        SrcFFEOP;
  output        SrcFFErr;
  input         SrcFFAlmostFull_n;
  output        SrcFFWrEn_n;
  input  [31:0] SrcStat;
  output [3:0]  SrcStatAddr;
  input  [7:0]  SrcStatCh;
  input         SrcStatChValid;

  output [31:0] SnkStat;
  output [3:0]  SnkStatAddr;
  output        SnkStatWr_n;
  output [15:0] SnkStatMask;
  
  wire          Reset_n;
  wire          LoopbackClk;
  wire          LoopbackEn_n;
  wire  [31:0] SnkFFData;
  wire    [1:0] SnkFFMod;
  wire    [7:0] SnkFFAddr;
  wire          SnkFFSOP;
  wire          SnkFFEOP;
  wire          SnkFFErr;
  wire          SnkFFAlmostEmpty_n;
  wire          SnkFFEmpty_n;
  wire          SnkFFValid;
  wire          SnkFFRdEn_n;
  wire  [31:0] SrcFFData;
  wire    [1:0] SrcFFMod;
  wire    [7:0] SrcFFAddr;
  wire          SrcFFSOP;
  wire          SrcFFEOP;
  wire          SrcFFErr;
  wire          SrcFFAlmostFull_n;
  wire          SrcFFWrEn_n;

  wire  [3:0]   SrcStatAddr;
  wire  [31:0]  SrcStat;
  wire  [7:0]   SrcStatCh;
  wire          SrcStatChValid;

  wire  [31:0] SnkStat;
  reg   [3:0]  SnkStatAddr;
  reg          SnkStatWr_n;
  reg   [15:0] SnkStatMask;

  //***************************************************************************
  // Signal Declarations
  //***************************************************************************
  wire  [31:0] Data;
  wire    [1:0] Mods;
  wire    [7:0] Addr;
  wire          SOP;
  wire          EOP;
  wire          Err;
  wire          RReq;
  wire          RAck;

  //**************************************************************************
  // Parameter Declarations
  //**************************************************************************
  parameter TFF = 1000;

  
  //***************************************************************************
  // Instantiate the Loopback Write Module
  //***************************************************************************
  pl4_lite_fifo_loopback_write Write_Module(
    .Reset_n           (Reset_n),
    .LoopbackClk       (LoopbackClk),
    .LoopbackEn_n      (LoopbackEn_n),
    .RReq              (RReq),
    .RAck              (RAck),
    .Data              (Data),
    .Addr              (Addr),
    .Mods              (Mods),
    .SOP               (SOP),
    .EOP               (EOP),
    .Err               (Err),
    .SrcFFData         (SrcFFData),
    .SrcFFAddr         (SrcFFAddr),
    .SrcFFMod          (SrcFFMod),
    .SrcFFSOP          (SrcFFSOP),
    .SrcFFEOP          (SrcFFEOP),
    .SrcFFErr          (SrcFFErr),
    .SrcFFAlmostFull_n (SrcFFAlmostFull_n),
    .SrcFFWrEn_n       (SrcFFWrEn_n)
    );
  
  //***************************************************************************
  // Instantiate the Loopback Read Module
  //***************************************************************************
  pl4_lite_fifo_loopback_read Read_Module(
    .Reset_n            (Reset_n),
    .LoopbackClk        (LoopbackClk),
    .LoopbackEn_n       (LoopbackEn_n),
    .RReq               (RReq),
    .RAck               (RAck),
    .SnkFFData          (SnkFFData),
    .SnkFFAddr          (SnkFFAddr),
    .SnkFFMod           (SnkFFMod),
    .SnkFFSOP           (SnkFFSOP),
    .SnkFFEOP           (SnkFFEOP),
    .SnkFFErr           (SnkFFErr),
    .SnkFFValid         (SnkFFValid),
    .SnkFFAlmostEmpty_n (SnkFFAlmostEmpty_n),
    .SnkFFEmpty_n       (SnkFFEmpty_n),
    .SnkFFRdEn_n        (SnkFFRdEn_n),
    .Data               (Data),
    .Addr               (Addr),
    .Mods               (Mods),
    .SOP                (SOP),
    .EOP                (EOP),
    .Err                (Err)
    );



  //***************************************************************************
  //  the Source Status Signal to the Sink Status Signal
  //***************************************************************************
  assign SrcStatAddr = SrcStatCh[7:4];
  assign SnkStat     = SrcStat;

  always @ (negedge Reset_n or posedge StatLoopbackClk)
    begin:stat
      if (!Reset_n)
       begin
         SnkStatAddr       <= #TFF 4'b0;
         SnkStatWr_n       <= #TFF 1'b1;
         SnkStatMask       <= #TFF 16'b0;
       end
      else
       begin
         SnkStatAddr       <= #TFF SrcStatCh[7:4];
         SnkStatWr_n       <= #TFF ~SrcStatChValid;
         SnkStatMask       <= #TFF 16'hffff;
       end 

    end 

endmodule