uart232_top.v

spi接口的vhdl实现

  assign NumTrainSequences = 4 ;
  assign NumDip2Errors     = 4 ;
  assign NumDip2Matches    = 4 ;
  assign SnkAFThresAssert  = 32 ;
  assign SnkAFThresNegate  = 32 ;
  assign SrcAFThresAssert  = 32 ;
  assign SrcAFThresNegate  = 32 ;
  assign FifoAFMode        = 2'b01;
  assign DataMaxT          = 4096 ;
  assign AlphaData         = 2 ;
  assign RSClkPhase        = 1'b0 ;
  assign RSClkDiv          = 1'b0 ;
  assign SnkCalendar_Len   = 15 ;
  assign SnkCalendar_M     = 0 ;
  assign SrcBurstLen       = 32 ;
  assign SrcBurstMode      = 1'b1 ;
  assign SrcCalendar_Len   = 15 ;
  assign SrcCalendar_M     = 0 ;


  
  assign SnkFFEmpty_n = SnkFFEmpty_n_i;


  //****************************************************************************
  // Instantiate LVDS IBUF for the status pins
  //****************************************************************************
  IBUFDS  TStat_ibuf0(
    .I  (TStat_P[0]),
    .IB (TStat_N[0]),
    .O  (TStat_i[0])
     );

// XST Synthesis Attributes
// synthesis attribute  TStat_ibuf0 IBUF_DELAY_VALUE of  TStat_ibuf0 is "0"
// synthesis attribute  TStat_ibuf0 IFD_DELAY_VALUE of   TStat_ibuf0 is "0"


// synthesis translate_off
    defparam  TStat_ibuf0.IBUF_DELAY_VALUE   ="0";
    defparam  TStat_ibuf0.IFD_DELAY_VALUE    ="0";

// synthesis translate_on



  IBUFDS  TStat_ibuf1(
    .I  (TStat_P[1]),
    .IB (TStat_N[1]),
    .O  (TStat_i[1])
     );

// XST Synthesis Attributes
// synthesis attribute  IBUF_DELAY_VALUE of  TStat_ibuf1 is "0"
// synthesis attribute  IFD_DELAY_VALUE of   TStat_ibuf1 is "0"


// synthesis translate_off
    defparam  TStat_ibuf1.IBUF_DELAY_VALUE   ="0";
    defparam  TStat_ibuf1.IFD_DELAY_VALUE    ="0";

// synthesis translate_on



  IBUFGDS  TSClk_ibufg0(
    .I  (TSClk_P),
    .IB (TSClk_N),
    .O  (TSClk_i)
   );

  //****************************************************************************
  // Instantiate LVDS OBUF for the RStat and RSClk pins
  //****************************************************************************
  OBUFTDS  RStat_obuf0(
    .I  (RStat_i[0]),
    .T (SnkTriStateEn),
    .O  (RStat_P[0]),
    .OB (RStat_N[0])
   );

  OBUFTDS  RStat_obuf1(
    .I  (RStat_i[1]),
    .T (SnkTriStateEn),
    .O  (RStat_P[1]),
    .OB (RStat_N[1])
   );

  OBUFTDS  RSClk_obuf0(
    .I  (RSClk_i),
    .T (SnkTriStateEn),
    .O  (RSClk_P),
    .OB (RSClk_N)
   );


  //****************************************************************************
  // CalClk_bufg0
  //****************************************************************************
  // BUFG instantiation for the CalClk clock input
  //****************************************************************************
  IBUFG CalClk_ibufg0(
    .I (CalClk),
    .O (CalClk_ibufg)
   );

  BUFG CalClk_bufg0(
    .I (CalClk_ibufg),
    .O (CalClk_bufg)
   );

  //****************************************************************************
  // LoopbackClk_bufg0
  //****************************************************************************
  // BUFG instantiation for the LoopbackClk clock input
  //****************************************************************************
  IBUFG LoopbackClk_ibufg0(
    .I (LoopbackClk),
    .O (LoopbackClk_ibufg)
   );

  BUFG LoopbackClk_bufg0(
    .I (LoopbackClk_ibufg),
    .O (LoopbackClk_bufg)
   );


  //****************************************************************************
  // Pipeline calendar input signals
  // These signals must be driven from registers
  //****************************************************************************
  always @ (negedge Reset_n or posedge CalClk_bufg)
  begin
    if (!Reset_n)
      begin
        SnkCalWrEn_n_r1 <= #TFF 1'b1;
        SnkCalWrEn_n_r2 <= #TFF 1'b1;
        SnkCalAddr_r1   <= #TFF 9'h00;
        SnkCalAddr_r2   <= #TFF 9'h00;
        SnkCalData_r1   <= #TFF 8'h00;
        SnkCalData_r2   <= #TFF 8'h00;

        SrcCalWrEn_n_r1 <= #TFF 1'b1;
        SrcCalWrEn_n_r2 <= #TFF 1'b1;
        SrcCalAddr_r1   <= #TFF 9'h00;
        SrcCalAddr_r2   <= #TFF 9'h00;
        SrcCalData_r1   <= #TFF 8'h00;
        SrcCalData_r2   <= #TFF 8'h00;
      end
    else
      begin
        SnkCalWrEn_n_r1 <= #TFF SnkCalWrEn_n;
        SnkCalWrEn_n_r2 <= #TFF SnkCalWrEn_n_r1;
        SnkCalAddr_r1   <= #TFF SnkCalAddr;
        SnkCalAddr_r2   <= #TFF SnkCalAddr_r1;
        SnkCalData_r1   <= #TFF SnkCalData;
        SnkCalData_r2   <= #TFF SnkCalData_r1;

        SrcCalWrEn_n_r1 <= #TFF SrcCalWrEn_n;
        SrcCalWrEn_n_r2 <= #TFF SrcCalWrEn_n_r1;
        SrcCalAddr_r1   <= #TFF SrcCalAddr;
        SrcCalAddr_r2   <= #TFF SrcCalAddr_r1;
        SrcCalData_r1   <= #TFF SrcCalData;
        SrcCalData_r2   <= #TFF SrcCalData_r1;
      end
  end


  //****************************************************************************
  // pl4_lite_snk_top component instantiation.
  //****************************************************************************
 uart232_pl4_lite_snk_top uart232_pl4_lite_snk_top0(
    // common signals
    .reset_n            (Reset_n),
    .snkfiforeset_n     (SnkFifoReset_n),

     .dcmlost_rdclk      (DcmLost_RDClk),
    .dcmreset_rdclk     (DcmReset_RDClk),
    .locked_rdclk       (Locked_RDClk),

    .snkclksrdy         (SnkClksRdy),

    // sink general purpose clocks
    .rdclk0_gp          (),
    .rdclk180_gp        (),
 
    // Sink Calendar I/O
    .snkcalendar_m      (SnkCalendar_M),
    .snkcalendar_len    (SnkCalendar_Len),
    .snkcalclk          (CalClk_bufg),
    .snkcalwren_n       (SnkCalWrEn_n_r2),
    .snkcaladdr         (SnkCalAddr_r2),
    .snkcaldata         (SnkCalData_r2),
    .snkcaldataout      (SnkCalDataOut),
    .snkstatclk         (CalClk_bufg),
    .snkstat            (SnkStat),
    .snkstataddr        (SnkStatAddr),
    .snkstatwr_n        (SnkStatWr_n),
    .snkstatmask        (SnkStatMask),

    // FIFO I/O
    .snkffclk           (LoopbackClk_bufg),
    .snkffrden_n        (SnkFFRdEn_n),
    .snkffaddr          (SnkFFAddr),
    .snkffdata          (SnkFFData),
    .snkffmod           (SnkFFMod),
    .snkffsop           (SnkFFSOP),
    .snkffeop           (SnkFFEOP),
    .snkffbursterr      (SnkFFBurstErr),
    .snkfferr           (SnkFFErr),
    .snkffdip4err       (SnkFFDIP4Err),
    .snkffpayloaderr    (SnkFFPayloadErr),
    .snkffpayloaddip4   (SnkFFPayloadDIP4),

    .snkffvalid         (SnkFFValid),
    .snkffempty_n       (SnkFFEmpty_n_i),
    .snkffalmostempty_n (SnkFFAlmostEmpty_n),
    .snkalmostfull_n    (SnkAlmostFull_n),
    .snkoverflow_n      (SnkOverflow_n),

    // Control and status signals
    .snken              (SnkEn),
    .snkoof             (SnkOof),
    .snkbuserr          (SnkBusErr),
    .snkbuserrstat      (SnkBusErrStat),
    .snktrainvalid      (SnkTrainValid),
    .snkdip2errrequest  (SnkDIP2ErrRequest),

    // FIFO status interface
    .rsclk              (RSClk_i),
    .rstat              (RStat_i),

    // PL4 sink bus
     .rdclk_p            (RDClk_P),
    .rdclk_n            (RDClk_N),
     .rdat_p             (RDat_P),
    .rdat_n             (RDat_N),
    .rctl_p             (RCtl_P),
    .rctl_n             (RCtl_N),

    // Configuration signals
    .snkafthresassert   (SnkAFThresAssert),
    .snkafthresnegate   (SnkAFThresNegate),
    .fifoafmode         (FifoAFMode),
    .numdip4errors      (NumDip4Errors),
    .numtrainsequences  (NumTrainSequences),
    .rsclkphase         (RSClkPhase),
    .rsclkdiv           (RSClkDiv)
    );

  //****************************************************************************
  // pl4_lite_src_top component instantiation.
  //****************************************************************************
  uart232_pl4_lite_src_top uart232_pl4_lite_src_top0(
     // common signals
    .reset_n              (Reset_n),
    .srctristateen        (SrcTriStateEn),
    .srcfiforeset_n       (SrcFifoReset_n),
    .dcmreset_tdclk       (DcmReset_TDClk),
    .locked_tdclk         (Locked_TDClk),
    .dcmlost_tdclk        (DcmLost_TDClk),
    .srcclksrdy           (SrcClksRdy),
    .sysclk_p             (SysClk_P),
    .sysclk_n             (SysClk_N),

    // source general purpose clocks
    .tsclk_gp             (TSClk_GP_i),
    .sysclk0_gp           (),
    .sysclk180_gp         (),

    // Source Calendar I/O
    .srccalendar_m        (SrcCalendar_M),
    .srccalendar_len      (SrcCalendar_Len),
    .srccalclk            (CalClk_bufg),
    .srccalwren_n         (SrcCalWrEn_n_r2),
    .srccaladdr           (SrcCalAddr_r2),
    .srccaldata           (SrcCalData_r2),
    .srccaldataout        (SrcCalDataOut),

    .srcstatclk           (CalClk_bufg),
    .srcstataddr          (SrcStatAddr),

    .srcstat              (SrcStat),
    .srcstatch            (SrcStatCh),
    .srcstatchvalid       (SrcStatChValid),

    // FIFO I/O
    .srcffclk             (LoopbackClk_bufg),
    .srcffwren_n          (SrcFFWrEn_n),
    .srcffaddr            (SrcFFAddr),
    .srcffdata            (SrcFFData),
    .srcffmod             (SrcFFMod),
    .srcffsop             (SrcFFSOP),
    .srcffeop             (SrcFFEOP),
    .srcfferr             (SrcFFErr),
    .srcffoverflow_n      (SrcFFOverflow_n),
    .srcffalmostfull_n    (SrcFFAlmostFull_n),

    // Control and status signals
    .srcen                (SrcEn),
    .idlerequest          (IdleRequest),
    .trainingrequest      (TrainingRequest),
    .srcoofoverride       (SrcOofOverride),
    .srcoof               (SrcOof),
    .srcdip2err           (SrcDIP2Err),
    .srcstatframeerr      (SrcStatFrameErr),
    .srcpatternerr        (SrcPatternErr),

    // FIFO status interface
    .tsclk                (TSClk_i),
    .tstat                (TStat_i),

    // PL4 source bus
    .tdclk_p              (TDClk_P),
    .tdclk_n              (TDClk_N),
    .tdat_p               (TDat_P),
    .tdat_n               (TDat_N),
    .tctl_p               (TCtl_P),
    .tctl_n               (TCtl_N),

    // Configuration signals
    .srcafthresassert     (SrcAFThresAssert),
    .srcafthresnegate     (SrcAFThresNegate),
    .datamaxt             (DataMaxT),
    .alphadata            (AlphaData),
    .srcburstlen          (SrcBurstLen),
    .srcburstmode         (SrcBurstMode),
    .numdip2errors        (NumDip2Errors),
    .numdip2matches       (NumDip2Matches)

    );

  //****************************************************************************
  // fifo_loopback component instantiation.
  //****************************************************************************
  pl4_lite_fifo_loopback pl4_lite_fifo_loopback0(
    .Reset_n              (Reset_n),
    .LoopbackClk          (LoopbackClk_bufg),
    .StatLoopbackClk      (CalClk_bufg),

    .LoopbackEn_n         (LoopbackEn_n),

    // PL4 Sink interface
    .SnkFFAddr            (SnkFFAddr),
    .SnkFFData            (SnkFFData),
    .SnkFFSOP             (SnkFFSOP),
    .SnkFFEOP             (SnkFFEOP),
    .SnkFFMod             (SnkFFMod),
    .SnkFFErr             (SnkFFErr),
    .SnkFFRdEn_n          (SnkFFRdEn_n),
    .SnkFFEmpty_n         (SnkFFEmpty_n_i),
    .SnkFFAlmostEmpty_n   (SnkFFAlmostEmpty_n),
    .SnkFFValid           (SnkFFValid),

    // PL4 Source interface
    .SrcFFWrEn_n         (SrcFFWrEn_n),
    .SrcFFAddr           (SrcFFAddr),
    .SrcFFData           (SrcFFData),
    .SrcFFSOP            (SrcFFSOP),
    .SrcFFEOP            (SrcFFEOP),
    .SrcFFMod            (SrcFFMod),
    .SrcFFErr            (SrcFFErr),
    .SrcFFAlmostFull_n   (SrcFFAlmostFull_n),

    // Status loopback signals
    .SrcStatAddr         (SrcStatAddr),
    .SrcStat             (SrcStat),
    .SrcStatCh           (SrcStatCh),
    .SrcStatChValid      (SrcStatChValid),

    .SnkStat             (SnkStat),
    .SnkStatAddr         (SnkStatAddr),
    .SnkStatWr_n         (SnkStatWr_n),
    .SnkStatMask         (SnkStatMask)
   );



endmodule