uart232_top.v

spi接口的vhdl实现

//****************************************************************************
// PL4 Level Wrapper Verilog RTL Design
//****************************************************************************
//
// This file is owned and controlled by Xilinx and must be used solely
// for design, simulation, implementation and creation of design files
// limited to Xilinx devices or technologies. Use with non*Xilinx
// devices or technologies is expressly prohibited and immediately
// terminates your license.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications is
// expressly prohibited.
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_wrapper.v
//
// Description:  This file contains an example implementation of the PL4 core,
// instantiating the PL4 Sink core, PL4 Source core, and FIFO Loopback. This
// implementation also has synthesis attributes for Synplicity, Exemplar,
// and XST.
//
//*****************************************************************************
// Alternative DPA Simulation Model
//*****************************************************************************
// In addition to the cycle accurate DPA simulation model, there is a shortened
// alignment simulation model which can be use to decrease functional
// simulation time.  To use the shortened alignment simulation model, this file
// and the simulation script (simulate_*.*) must be modified.
// References to the component "uart232_pl4_lite_snk_top"
// must be replaced with "pl4_lite_snk_top".
//
// This file contains commented out lines, which can be uncommented to
// use the shortened alignment simulation model.  To find the lines which need
// to be commented/uncommented search for "DPA".  See Chapter 8 of the User
// Guide for more information on using the shortened alignment simulation
// models.
//*****************************************************************************
// Structure: pl4_lite_wrapper.v
//               |
//               +-- pl4_lite_snk_top (Sink Core EDIF file)
//               |
//               +-- pl4_lite_fifo_loopback.v
//               |           |
//               |           +--- pl4_lite_fifo_loopback_read.v
//               |           |
//               |           +--- pl4_lite_fifo_loopback_write.v
//               |
//               |
//               +-- pl4_lite_src_top (Source Core EDIF file)
//
//*****************************************************************************

`timescale 1ps/1ps


//******************************************************************************
// Top Module Declaration
//******************************************************************************
module pl4_lite_wrapper (
    //**************************************************************************
    // Common signals
    //**************************************************************************
    Reset_n,
    CalClk,
    LoopbackClk,

    //**************************************************************************
    // PL4 Sink signals
    //**************************************************************************
    // PL4 Sink bus inputs
    RDClk_P,
    RDClk_N,
    RCtl_P,
    RCtl_N,
    RDat_P,
    RDat_N,

    //PL4 sink status outputs in LVDS
    RSClk_P,
    RSClk_N,
    RStat_P,
    RStat_N,

    // Control signals
    SnkEn,
    SnkTriStateEn,
    SnkFifoReset_n,

    // Sink status signals
    SnkOof,
    SnkBusErr,
    SnkBusErrStat,
    SnkTrainValid,
    SnkDIP2ErrRequest,

    SnkAlmostFull_n,
    SnkOverflow_n,
    SnkFFEmpty_n,

    // Sink user interface status signals
    SnkFFDIP4Err,
    SnkFFBurstErr,
    SnkFFPayloadErr,
    SnkFFPayloadDIP4,

    // Sink Calendar signals
    SnkCalWrEn_n,
    SnkCalAddr,
    SnkCalData,
    SnkCalDataOut,


    // Sink DCM signals
    DcmReset_RDClk,
    Locked_RDClk,
    DcmLost_RDClk,
    SnkClksRdy,

    //**************************************************************************
    // PL4 Source signals
    //**************************************************************************
    // Clock input
    SysClk_P,
    SysClk_N,

    // PL4 source bus outputs
    TDClk_P,
    TDClk_N,
    TCtl_P,
    TCtl_N,
    TDat_P,
    TDat_N,

    // PL4 source status inputs in LVDS
    TSClk_P,
    TSClk_N,
    TStat_P,
    TStat_N,

    // Control signals
    SrcEn,
    SrcTriStateEn,
    SrcFifoReset_n,
    IdleRequest,
    TrainingRequest,

    // Source Calendar signals
    SrcCalWrEn_n,
    SrcCalAddr,
    SrcCalData,
    SrcCalDataOut,

    // Source Calendar status signals
    SrcOofOverride,
    SrcOof,
    SrcDIP2Err,
    SrcStatFrameErr,

    // Source status signal
    SrcPatternErr,
    SrcFFAlmostFull_n,
    SrcFFOverflow_n,

    // Source DCM signals
    DcmReset_TDClk,
    Locked_TDClk,
    DcmLost_TDClk,
    SrcClksRdy
   ) /*synthesis syn_edif_bit_format="%n(%i)" syn_noclockbuf = 1 */;

  //****************************************************************************
  // I/O declarations
  //****************************************************************************
  input         Reset_n;
  input         CalClk;
  input         LoopbackClk;
  input         RDClk_P;
  input         RDClk_N;
  input         RCtl_P;
  input         RCtl_N;
  input  [15:0] RDat_P;
  input  [15:0] RDat_N;
  output        RSClk_P;
  output        RSClk_N;
  output  [1:0] RStat_P;
  output  [1:0] RStat_N;

  input         SnkEn;
  input         SnkTriStateEn;
  input         SnkFifoReset_n;

  output        SnkOof;
  output        SnkBusErr;
  output  [7:0] SnkBusErrStat;
  output        SnkTrainValid;
  input         SnkDIP2ErrRequest;

  output        SnkAlmostFull_n;
  output        SnkOverflow_n;
  output        SnkFFEmpty_n;

  output        SnkFFDIP4Err;
  output        SnkFFBurstErr;
  output        SnkFFPayloadErr;
  output        SnkFFPayloadDIP4;

  input         SnkCalWrEn_n;
  input   [8:0] SnkCalAddr;
  input   [7:0] SnkCalData;
  output  [7:0] SnkCalDataOut;

  input         DcmReset_RDClk;
  output        Locked_RDClk;
  output        DcmLost_RDClk;
  output        SnkClksRdy;

  input         SysClk_P;
  input         SysClk_N;
  output        TDClk_P;
  output        TDClk_N;
  output        TCtl_P;
  output        TCtl_N;
  output [15:0] TDat_P;
  output [15:0] TDat_N;
  input         TSClk_P;
  input         TSClk_N;
  input   [1:0] TStat_P;
  input   [1:0] TStat_N;

  input         SrcEn;
  input         SrcTriStateEn;
  input         SrcFifoReset_n;
  input         IdleRequest;
  input         TrainingRequest;
  input         SrcCalWrEn_n;
  input   [8:0] SrcCalAddr;
  input   [7:0] SrcCalData;
  output  [7:0] SrcCalDataOut;

  input         SrcOofOverride;
  output        SrcOof;
  output        SrcDIP2Err;
  output        SrcStatFrameErr;
  output        SrcPatternErr;
  output        SrcFFAlmostFull_n;
  output        SrcFFOverflow_n;
  input         DcmReset_TDClk;
  output        Locked_TDClk;
  output        DcmLost_TDClk;
  output        SrcClksRdy;

  //****************************************************************************
  // Parameter Declarations
  //****************************************************************************
  parameter TFF = 1000;

  //****************************************************************************
  // Static Configuration Signal Declaration
  //****************************************************************************
  wire        LoopbackEn_n;
  wire  [3:0] NumDip4Errors;
  wire  [3:0] NumTrainSequences;
  wire  [3:0] NumDip2Errors;
  wire  [3:0] NumDip2Matches;

  wire  [8:0] SnkAFThresAssert;
  wire  [8:0] SnkAFThresNegate;

  wire  [8:0] SrcAFThresAssert;
  wire  [8:0] SrcAFThresNegate;
  wire  [1:0] FifoAFMode;
  wire [15:0] DataMaxT;
  wire  [7:0] AlphaData;
  wire        RSClkPhase;
  wire        RSClkDiv;

  wire  [8:0] SnkCalendar_Len;
  wire  [7:0] SnkCalendar_M;
  wire  [5:0] SrcBurstLen;
  wire        SrcBurstMode;
  wire  [8:0] SrcCalendar_Len;
  wire  [7:0] SrcCalendar_M;
  //****************************************************************************
  // Clock Buffer output signal
  //****************************************************************************
  wire        CalClk_ibufg;
  wire        LoopbackClk_ibufg;

  wire        CalClk_bufg;
  wire        LoopbackClk_bufg;

  //****************************************************************************
  // Internal core interconnection signals
  //****************************************************************************
  // PL4 Sink FIFO Interface
  wire        SnkFFRdEn_n;
  wire  [7:0] SnkFFAddr;
  wire [31:0] SnkFFData;
  wire  [1:0] SnkFFMod;
  wire        SnkFFSOP;
  wire        SnkFFEOP;
  wire        SnkFFErr;
  wire        SnkFFValid;
  wire [31:0] SnkStat;
  wire [3:0]  SnkStatAddr;
  wire        SnkStatWr_n;
  wire [15:0] SnkStatMask;

  wire        SnkFFAlmostEmpty_n;
  wire        SnkFFEmpty_n_i;

  wire  [1:0] RStat_i;
  wire        RSClk_i;


  // PL4 Source FIFO Interface
  wire        SrcFFWrEn_n;
  wire  [7:0] SrcFFAddr;

  wire [31:0] SrcFFData;
  wire  [1:0] SrcFFMod;
  wire        SrcFFSOP;
  wire        SrcFFEOP;
  wire        SrcFFErr;
  wire [31:0] SrcStat;
  wire [3:0]  SrcStatAddr;
  wire        SrcStatChValid;
  wire [7:0]  SrcStatCh;
  wire        SrcFFAlmostFull_n;
  wire        SrcFFAlmostFull_n_i;
  wire        SrcFFOverflow_n;

  wire  [1:0] TStat_i;
  wire        TSClk_i;
  wire        TSClk_GP_i;

  // PL4 Calendar Interface
  reg         SnkCalWrEn_n_r1;
  reg         SnkCalWrEn_n_r2;
  reg   [8:0] SnkCalAddr_r1;
  reg   [8:0] SnkCalAddr_r2;
  reg   [7:0] SnkCalData_r1;
  reg   [7:0] SnkCalData_r2;
  reg         SrcCalWrEn_n_r1;
  reg         SrcCalWrEn_n_r2;
  reg   [8:0] SrcCalAddr_r1;
  reg   [8:0] SrcCalAddr_r2;
  reg   [7:0] SrcCalData_r1;
  reg   [7:0] SrcCalData_r2;



  //****************************************************************************
  // XST Inhibit pad insertion synthesis attributes
  //****************************************************************************
  //synthesis attribute clock_buffer of SysClk_P is none;
  //synthesis attribute clock_buffer of SysClk_N is none;
  //synthesis attribute clock_buffer of RDClk_P  is none;
  //synthesis attribute clock_buffer of RDClk_N  is none;
  //synthesis attribute clock_buffer of RDat_P   is none;
  //synthesis attribute clock_buffer of RDat_N   is none;
  //synthesis attribute clock_buffer of RCtl_P   is none;
  //synthesis attribute clock_buffer of RCtl_N   is none;
  //synthesis attribute clock_buffer of TDClk_P  is none;
  //synthesis attribute clock_buffer of TDClk_N  is none;
  //synthesis attribute clock_buffer of TDat_P   is none;
  //synthesis attribute clock_buffer of TDat_N   is none;
  //synthesis attribute clock_buffer of TCtl_P   is none;
  //synthesis attribute clock_buffer of TCtl_N   is none;

  //synthesis attribute box_type of uart232_pl4_lite_snk_top is black_box;
  //synthesis attribute box_type of uart232_pl4_lite_src_top is black_box;
  //****************************************************************************
  // The following signal instantiations are the Static Configuration signals.
  //****************************************************************************
  assign LoopbackEn_n      = 1'b0;
  assign NumDip4Errors     = 4 ;