pl4_lite_fifo_loopback_read.v

spi接口的vhdl实现

//****************************************************************************
// PL4 FIFO Loopback Read Verilog RTL Design
//****************************************************************************
//                                                                       
// This file is owned and controlled by Xilinx and must be used solely   
// for design, simulation, implementation and creation of design files   
// limited to Xilinx devices or technologies. Use with non*Xilinx        
// devices or technologies is expressly prohibited and immediately       
// terminates your license.                                              
//                                                                       
// Xilinx products are not intended for use in life support              
// appliances, devices, or systems. Use in such applications is          
// expressly prohibited.                                                 
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_fifo_loopback_read.v
//*****************************************************************************
// Structure: pl4_lite_fifo_loopback_read.v
//*****************************************************************************
// Description:  This code implements a synthesizable FIFO loopback read 
// state machine for the PL4 Sink Core.
//*****************************************************************************

`timescale 1ps/1ps

module pl4_lite_fifo_loopback_read(
  //*************************************************************************
  // Common Signals
  //*************************************************************************
  Reset_n,
  LoopbackClk,
  LoopbackEn_n,
  RReq,
  RAck,

  //**************************************************************************
  // PL4 Sink Signals
  //**************************************************************************
  SnkFFData,
  SnkFFAddr,
  SnkFFMod,
  SnkFFSOP,
  SnkFFEOP,
  SnkFFErr,
  SnkFFValid,
  SnkFFAlmostEmpty_n,
  SnkFFEmpty_n,
  SnkFFRdEn_n,

  //**************************************************************************
  // PL4 Source Signals
  //**************************************************************************
  Data,
  Addr,
  Mods,
  SOP,
  EOP,
  Err
  );

  input         Reset_n;
  input         LoopbackClk;    
  input         LoopbackEn_n; 
  input         RReq;
  output        RAck;
  input [31:0] SnkFFData;
  input   [1:0] SnkFFMod;
  input   [7:0] SnkFFAddr;
  input         SnkFFSOP;
  input         SnkFFEOP;
  input         SnkFFErr;
  input         SnkFFValid;
  input         SnkFFAlmostEmpty_n;
  input         SnkFFEmpty_n;
  output        SnkFFRdEn_n;
  output [31:0] Data;
  output   [1:0] Mods;
  output  [7:0] Addr;
  output        SOP;
  output        EOP;
  output        Err;

  wire          Reset_n;
  wire          LoopbackClk;    
  wire          LoopbackEn_n; 
  wire          RReq;
  wire          RAck;
  wire  [31:0] SnkFFData;
  wire    [1:0] SnkFFMod;
  wire    [7:0] SnkFFAddr;
  wire          SnkFFSOP;
  wire          SnkFFEOP;
  wire          SnkFFErr;
  wire          SnkFFValid;
  wire          SnkFFAlmostEmpty_n;
  wire          SnkFFEmpty_n;
  reg           SnkFFRdEn_n;
  wire  [31:0] Data;
  wire    [1:0] Mods;
  wire    [7:0] Addr;
  wire          SOP;
  wire          EOP;
  wire          Err;

  //**************************************************************************
  // Parameter Declarations
  //**************************************************************************
  parameter TFF = 1000;

  //**************************************************************************
  // State Machine Parameter Declarations
  // StateType: 
  //    IDLE             - Reset and idle state.
  //    REQUEST          - A data transfer request. This indicates that the
  //                       loopback is enabled, the Sink FIFO has data, and
  //                       the Source FIFO can accept data.
  //    TRANSFER         - Data is transferred in this state. Remain in this
  //                       state until the loopback is disabled, the Sink FIFO
  //                       doesn't have any more data, or the Source FIFO
  //                       cannot accept any more data.
  //    ONE_TRANSFER     - Indicates that the Sink FIFO has only one word
  //                       available for reading.
  //
  // Register:
  //    State   - holds current state of state machine
  //**************************************************************************
  parameter IDLE         = 4'b0001;
  parameter REQUEST      = 4'b0010;
  parameter TRANSFER     = 4'b0100;
  parameter ONE_TRANSFER = 4'b1000;


  //**************************************************************************
  // Register Declarations
  //**************************************************************************
  reg [3:0] State;
  reg       OneWordLeft;
  reg       SnkFFEmpty_n_r;
  reg       SnkFFAlmostEmpty_n_r;

  //**************************************************************************
  // Drive out the inputs from the Sink FIFO.
  //**************************************************************************
  assign Data = SnkFFData;
  assign Addr = SnkFFAddr;
  assign Mods = SnkFFMod;
  assign SOP  = SnkFFSOP;
  assign EOP  = SnkFFEOP;
  assign Err  = SnkFFErr;
  assign RAck = SnkFFValid;

  //**************************************************************************
  // Determine if only one word is left in the FIFO. This is true only if 
  // Empty_n was asserted on the previous cycle, and AlmostEmpty_n is not 
  // asserted on the current cycle.
  //**************************************************************************
  always @ (negedge Reset_n or posedge LoopbackClk)
    begin:reg_empty
      if (!Reset_n)
        begin
        SnkFFEmpty_n_r <= #TFF 1'b0;
        SnkFFAlmostEmpty_n_r <= #TFF 1'b0;
        end
      else
        begin
        SnkFFEmpty_n_r <= #TFF SnkFFEmpty_n;
        SnkFFAlmostEmpty_n_r <= #TFF SnkFFAlmostEmpty_n;
        end
    end

  // In order for only one word left to be true, then not AE_n and E_n needs
  // to be true for at least two cycles. This prevents flagging an incorrect
  // one word left indication as the FIFO is transitioning from E to AE.
  always @ (negedge Reset_n or posedge LoopbackClk)
    begin:one_left
      if (!Reset_n)
        OneWordLeft <= #TFF 1'b0;
      else
        OneWordLeft <= #TFF (!SnkFFAlmostEmpty_n & SnkFFEmpty_n &
                            !SnkFFAlmostEmpty_n_r & SnkFFEmpty_n_r);
    end

  //**************************************************************************
  // State Machine Process
  //**************************************************************************
  always @ (negedge Reset_n or posedge LoopbackClk )
  begin:state_machine
    if (!Reset_n)
      begin
      State       <= #TFF IDLE;
      SnkFFRdEn_n <= #TFF 1'b1;
      end
    else
      begin
        case (State)
          //******************************************************************
          // State 0: IDLE 
          //******************************************************************
          IDLE:
            begin
              if (SnkFFAlmostEmpty_n & RReq & !LoopbackEn_n)
                begin
                  State       <= #TFF REQUEST;
                  SnkFFRdEn_n <= #TFF 1'b0;
                end
              else if (OneWordLeft & RReq & !LoopbackEn_n)
                begin
                  State       <= #TFF ONE_TRANSFER;
                  SnkFFRdEn_n <= #TFF 1'b0;
                end
              else
                begin
                  State       <= #TFF IDLE;
                  SnkFFRdEn_n <= #TFF 1'b1;
                end
            end

          //******************************************************************
          // State 1: REQUEST
          //******************************************************************
          REQUEST:
            begin
              State       <= #TFF TRANSFER;
              SnkFFRdEn_n <= #TFF 1'b0;
            end

          //******************************************************************
          // State 2: TRANSFER
          //******************************************************************
          TRANSFER:
            begin
              if (!LoopbackEn_n & SnkFFAlmostEmpty_n & RReq)
                begin
                  State       <= #TFF TRANSFER;
                  SnkFFRdEn_n <= #TFF 1'b0;
                end
              else
                begin
                  State       <= #TFF IDLE;
                  SnkFFRdEn_n <= #TFF 1'b1;
                end
            end

          //******************************************************************
          // State 3: ONE_TRANSFER
          //******************************************************************
          ONE_TRANSFER:
            begin
              State       <= #TFF IDLE;
              SnkFFRdEn_n <= #TFF 1'b1;
            end

          //******************************************************************
          // Error and Default States
          //******************************************************************
          default:
            begin
              State       <= #TFF IDLE;
              SnkFFRdEn_n <= #TFF 1'b1;
            end
        endcase
      end
  end
endmodule