uart232_pl4_lite_src_top.v

spi接口的vhdl实现

//****************************************************************************
// PL4 Source Verilog Module
//****************************************************************************
//
// This file is owned and controlled by Xilinx and must be used solely
// for design, simulation, implementation and creation of design files
// limited to Xilinx devices or technologies. Use with non*Xilinx
// devices or technologies is expressly prohibited and immediately
// terminates your license.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications is
// expressly prohibited.
//
//            **************************************
//            ** Copyright (C) 2001, Xilinx, Inc. **
//            ** All Rights Reserved.             **
//            **************************************
//
//*****************************************************************************
// Filename:  pl4_lite_src_top.v
//
// Description:  Module declaration for the Source Core
//
//*****************************************************************************

`timescale 1ps/1ps

//******************************************************************************
// PL4 Source Module Declaration
//******************************************************************************
module uart232_pl4_lite_src_top (
    // common signals
    reset_n,
    srctristateen,
    srcfiforeset_n,
    dcmreset_tdclk,
    locked_tdclk,
    dcmlost_tdclk,
    srcclksrdy,
    sysclk_p,
    sysclk_n,

    // source general purpose clocks
    sysclk180_gp,
    tsclk_gp,
    sysclk0_gp,

    // Source Calendar I/O
    srccalendar_m,
    srccalendar_len,
    srccalclk,
    srccalwren_n,
    srccaladdr,
    srccaldata,
    srccaldataout,

    srcstatclk,
    srcstataddr,
    srcstat,
    srcstatch,
    srcstatchvalid,

    // FIFO I/O
    srcffclk,
    srcffwren_n,
    srcffaddr,
    srcffdata,
    srcffmod,
    srcffsop,
    srcffeop,
    srcfferr,
    srcffoverflow_n,
    srcffalmostfull_n,

    // Control and status signals
    srcen,
    idlerequest,
    trainingrequest,
    srcoofoverride,
    srcoof,
    srcdip2err,
    srcstatframeerr,
    srcpatternerr,

    // FIFO status interface
    tsclk,
    tstat,

    // PL4 source bus
    tdclk_p,
    tdclk_n,
    tdat_p,
    tdat_n,
    tctl_p,
    tctl_n,

    // Configuration signals
    srcafthresassert,
    srcafthresnegate,
    datamaxt,
    alphadata,
    srcburstlen,
    srcburstmode,
    numdip2errors,
    numdip2matches
    ) /* synthesis syn_black_box */ ;

  //****************************************************************************
  // I/O declarations
  //****************************************************************************
  input         reset_n;
  input         srctristateen;
  input         srcfiforeset_n;
  input         dcmreset_tdclk;
  output        locked_tdclk;
  output        dcmlost_tdclk;
  output        srcclksrdy;
  input         sysclk_p   /* synthesis .ispad=1 */ ;
  input         sysclk_n   /* synthesis .ispad=1 */ ;
  output        sysclk180_gp;
  output        tsclk_gp;
  output        sysclk0_gp;
  input   [7:0] srccalendar_m;
  input   [8:0] srccalendar_len;
  input         srccalclk;
  input         srccalwren_n;
  input   [8:0] srccaladdr;
  input   [7:0] srccaldata;
  output  [7:0] srccaldataout;

  input         srcstatclk;
  output [31:0] srcstat;
  input  [3:0]  srcstataddr;
  output [7:0]  srcstatch;
  output        srcstatchvalid;
  input         srcffclk;
  input         srcffwren_n;
  input   [7:0] srcffaddr;
  input  [31:0] srcffdata;
  input   [1:0] srcffmod;
  input         srcffsop;
  input         srcffeop;
  input         srcfferr;
  output        srcffoverflow_n;
  output        srcffalmostfull_n;
  input         srcen;
  input         idlerequest;
  input         trainingrequest;
  input         srcoofoverride;
  output        srcoof;
  output        srcdip2err;
  output        srcstatframeerr;
  output        srcpatternerr;
  input         tsclk;
  input   [1:0] tstat;
  output        tdclk_p  /* synthesis .ispad=1 */ ;
  output        tdclk_n  /* synthesis .ispad=1 */ ;
  output [15:0] tdat_p   /* synthesis .ispad=1 */ ;
  output [15:0] tdat_n   /* synthesis .ispad=1 */ ;
  output        tctl_p   /* synthesis .ispad=1 */ ;
  output        tctl_n   /* synthesis .ispad=1 */ ;
  input   [8:0] srcafthresassert;
  input   [8:0] srcafthresnegate;
  input  [15:0] datamaxt;
  input   [7:0] alphadata;
  input   [5:0] srcburstlen;
  input         srcburstmode;
  input   [3:0] numdip2errors;
  input   [3:0] numdip2matches;

endmodule // pl4_lite_src_top