pl4_lite_clk_gen.v

spi接口的vhdl实现

/******************************************************************************
* SPI-4.2 Clock Generator
*******************************************************************************
*
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*
*******************************************************************************
* Filename: pl4_lite_clk_gen.v
*
* Description: This module defines the core level clocks that are used in
* the demonstration testbench for the SPI-4.2 core
*
*******************************************************************************
* Structure: pl4_lite_clk_gen.v
*
*****************************************************************************/
`timescale 1ps/1ps

/*****************************************************************************
* Library Declarations
*****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/*****************************************************************************
* Declare top-level module
*****************************************************************************/
module pl4_lite_clk_gen (
  Reset_n,
  TDClk,
  SysClk,
  RDClk2x,
  UserClk,
  TSClk
  );

input  Reset_n;
input  TDClk;

output SysClk;
output RDClk2x;
output UserClk;
output TSClk;

/****************************************************************************
* Definition of Ports
*****************************************************************************
* System Signals
*   Reset_n                    :  Input Reset (active low)
*   TDClk                      :  Input Clock from the core which is used
*                                 to create TSClk
*   SysClk                     :  Clock with period of TDClkPeriod which is
*                                 used in the control module and testcase
*                                 module
*   RDClk2x                    :  Clock with a period of half of RDClkPeriod
*                                 which is used in the control module and
*                                 testcase module
*   UserClk                    :  Clock with a period of UserClkPeriod
*                                 which is used for calendar programing and
*                                 in the Fifo Loopback module
*   TSClk                      :  Clock with a frequency of 1/4 TDClk
****************************************************************************/

/***************************************************************************
* Parameter Declarations
***************************************************************************/
parameter TDClkPeriod   = `TDCLK_PERIOD;
parameter RDClkPeriod   = `RDCLK_PERIOD;
parameter UserClkPeriod = `USERCLK_PERIOD;
/***************************************************************************
* Definition of Parameters:
*    TDClkPeriod                :  Period of TDClk
*    RDClkPeriod                :  Period of RDClk
*    UserClkPeriod              :  Period of UserClk
***************************************************************************/

/****************************************************************************
* Signal Declarations
****************************************************************************/
reg SysClk;
reg RDClk2x;
reg UserClk;
reg TSClk;
reg Div2;

/****************************************************************************
* Clock Creation
****************************************************************************/
  initial
    begin
      SysClk          = 1'b0;
      RDClk2x         = 1'b0;
      UserClk         = 1'b0;
      TSClk           = 1'b0;
      Div2            = 1'b0;
    end

  initial
    begin: Sysclk_gen
      forever #(TDClkPeriod/2) SysClk = !SysClk;
    end

  initial
    begin: RDClk2x_gen
      forever #(RDClkPeriod/4) RDClk2x = !RDClk2x;
    end

  initial
    begin: UserClk_gen
      forever #(UserClkPeriod/2) UserClk = !UserClk;
    end


  // TSClk generation: TSClk = TDClk / 4
  always @(posedge TDClk)
    begin: TDClkDiv2_gen
      Div2 = !Div2;
    end

  always @(posedge Div2)
    begin: TDClkDiv4_gen
      TSClk = !TSClk;
    end

endmodule