pl4_lite_demo_testbench.v

来自「spi接口的vhdl实现」· Verilog 代码 · 共 537 行 · 第 1/2 页

    // Sink Calendar signals
   .SnkCalWrEn_n       (SnkCalWrEn_n),
   .SnkCalAddr         (SnkCalAddr),
   .SnkCalData         (SnkCalData),
   .SnkCalDataOut      (SnkCalDataOut),

    // Sink DCM signals
   .DcmReset_RDClk     (DCMReset_RDClk),
   .Locked_RDClk       (Locked_RDClk),
   .DcmLost_RDClk      (),
   .SnkClksRdy         (SnkClksRdy),

   .SysClk_P           (SysClk_P),
   .SysClk_N           (SysClk_N),
   .TDClk_P            (TDClk_P),
   .TDClk_N            (TDClk_N),
   .TCtl_P             (TCtl_P),
   .TCtl_N             (TCtl_N),
   .TDat_P             (TDat_P),
   .TDat_N             (TDat_N),

   .TSClk_P            (TSClk_P),
   .TSClk_N            (TSClk_N),
   .TStat_P            (TStat_P),
   .TStat_N            (TStat_N),

    // Control signals
   .SrcEn              (SrcEn),
   .SrcTriStateEn      (zero),
   .SrcFifoReset_n     (SrcFifoReset_n),
   .IdleRequest        (IdleRequest),
   .TrainingRequest    (TrainingRequest),

    // Source Calendar signals
   .SrcCalWrEn_n       (SrcCalWrEn_n),
   .SrcCalAddr         (SrcCalAddr),
   .SrcCalData         (SrcCalData),
   .SrcCalDataOut      (SrcCalDataOut),

    // Source Calendar status signals
   .SrcOofOverride     (SrcOofOverride),
   .SrcOof             (SrcOof),
   .SrcDIP2Err         (SrcDIP2Err),
   .SrcStatFrameErr    (SrcStatFrameErr),

    // Source status signal
   .SrcPatternErr      (SrcPatternErr),
   .SrcFFAlmostFull_n  (),
   .SrcFFOverflow_n    (),

    // Source DCM signals
   .DcmReset_TDClk     (DCMReset_TDClk),
   .Locked_TDClk       (Locked_TDClk),
   .DcmLost_TDClk      (),
   .SrcClksRdy         (SrcClksRdy)
   );

  // Assign LVTTL output from wrapper to single-ended signal for testbench
  assign RSClk   = RSClk_P;
  assign RStat   = RStat_P;

  // Assign single-ended signal from testbench to LVTTL input of wrapper
  assign TSClk_P   = TSClk;
  assign TSClk_N   = ~TSClk;
  assign TStat_P   = TStat;
  assign TStat_N   = ~TStat;

/*****************************************************************************
* Instantiate stimulus module (takes test data from testcase and formats it
* for input to the Sink core)
*****************************************************************************/
pl4_lite_stimulus # (
  .SnkAlphaData         (`SNK_ALPHA_DATA),
  .SnkDataMaxT          (`SNK_DATA_MAX_T),
  .MergePayload         (`MERGE_PAYLOAD),
  .NumLinks             (`NUM_CHANNELS),
  .CheckRStat           (`CHECK_RSTAT),
  .DataType             (`DATA_TYPE),
  .RandomSeed           (`RANDOM_SEED)
  )
pl4_lite_stimulus0 (
  .SnkAlmostFull_n    (SnkAlmostFull_n), // rle
  .Reset_n              (Reset_n),
  .RDClk2x              (RDClk2x),
  .SysClk               (SysClk),
  .TSClkIn              (TSClkIn),
  .UserClk              (UserClk),
  .TCStat               (TCStat),
  .TCChannel            (TCChannel),
  .TCCtl                (TCCtl),
  .TCDat                (TCDat),
  .TCIdleRequest        (TCIdleRequest),
  .TCTrainingRequest    (TCTrainingRequest),
  .TCSnkDip2ErrRequest  (TCSnkDip2ErrRequest),
  .SrcCalendar_M        (SrcCalendar_M),
  .SrcCalendar_Len      (SrcCalendar_Len),
  .CtlFull              (CtlFull),
  .FFWriteEn            (FFWriteEn),
  .SopErr               (SopErr),
  .GetStatusChan        (GetStatusChan),
  .GetStatus            (GetStatus),
  .TCDIP2Request        (TCDIP2Request),
  .RDClk_P              (RDClk_P),
  .RDClk_N              (RDClk_N),
  .RDat_P               (RDat_P),
  .RDat_N               (RDat_N),
  .RCtl_P               (RCtl_P),
  .RCtl_N               (RCtl_N),
  .IdleRequest          (IdleRequest),
  .TrainingRequest      (TrainingRequest),
  .SnkDip2ErrRequest    (SnkDip2ErrRequest),
  .TStat                (TStat),
  .TSClk                (TSClk),
  .CalWrEn_n            (SrcCalWrEn_n),
  .CalAddr              (SrcCalAddr),
  .CalData              (SrcCalData),
  .SnkInFrame           (SnkInFrame),
  .SrcInFrame           (SrcInFrame)
);

/*****************************************************************************
* Instantiate startup module (controls sequencing of clocks and programming of
* calendars)
*****************************************************************************/
pl4_lite_startup #(
  .SnkCalDataFile      (`SNK_CAL_DATA),
  .SrcCalDataFile      (`SRC_CAL_DATA)
  )
pl4_lite_startup0 (
  .SysReset_n          (SysReset_n),
  .SPIClk              (SysClk),
  .UserClk             (UserClk),
  .DCMReset_RDClk      (DCMReset_RDClk),
  .Locked_RDClk        (Locked_RDClk),
  .SnkClksRdy          (SnkClksRdy),
  .DCMReset_TDClk      (DCMReset_TDClk),
  .Locked_TDClk        (Locked_TDClk),
  .SrcClksRdy          (SrcClksRdy),
  .Reset_n             (Reset_n),
  .SrcCalendar_Len     (SrcCalendar_Len),
  .SnkCalendar_Len     (SnkCalendar_Len),
  .SnkStatClk          (TSClkIn),
  .SrcStatClk          (TSClkIn),
  .SrcCalWrEn_n        (SrcCalWrEn_n),
  .SrcCalAddr          (SrcCalAddr),
  .SrcCalData          (SrcCalData),
  .SnkCalWrEn_n        (SnkCalWrEn_n),
  .SnkCalAddr          (SnkCalAddr),
  .SnkCalData          (SnkCalData),
  .SnkEn               (SnkEnStartup),
  .SrcEn               (SrcEnStartup)
);

/*****************************************************************************
* Instantiate testcase module (generates test data)
*****************************************************************************/
pl4_lite_testcase # (
  .CheckRStat           (`CHECK_RSTAT),
  .DataType             (`DATA_TYPE),
  .NumLinks             (`NUM_CHANNELS),
  .RandomSeed           (`RANDOM_SEED),
  .RDClkPeriod          (`RDCLK_PERIOD)
)
pl4_lite_testcase0 (
  .SysReset_n           (SysReset_n),
  .Reset_n              (Reset_n),
  .RDClk2x              (RDClk2x),
  .SysClk               (SysClk),
  .TSClk                (TSClk),
  .TCStat               (TCStat),
  .TCChan               (TCChannel),
  .TCCtl                (TCCtl),
  .TCDat                (TCDat),
  .TCIdleRequest        (TCIdleRequest),
  .TCTrainingRequest    (TCTrainingRequest),
  .TCSnkDip2ErrRequest  (TCSnkDip2ErrRequest),
  .TCComplete           (TCComplete),
  .CtlFull              (CtlFull),
  .FFWriteEn            (FFWriteEn),
  .SopErr               (SopErr),
  .GetStatusChan        (GetStatusChan),
  .GetStatus            (GetStatus),
  .TCDIP2Request        (TCDIP2Request),
  .SnkInFrame           (SnkInFrame),
  .SrcInFrame           (SrcInFrame),
  .FullVec              (FullVec),
  .SnkAlmostFull_n      (SnkAlmostFull_n), // rle
  .SnkOof               (SnkOof),
  .SrcOof               (SrcOof),
  .SnkEn                (SnkEnTC),
  .SrcEn                (SrcEnTC),
  .SnkFifoReset_n       (SnkFifoReset_n),
  .SrcFifoReset_n       (SrcFifoReset_n)
);

/*****************************************************************************
* Instantiate data monitor (monitors RDat & TDat to verify cores are
* behaving correctly)
*****************************************************************************/
pl4_lite_data_monitor pl4_lite_data_monitor0(
  .Reset_n              (Reset_n),
  .RCtl                 (RCtl_P),
  .RDat                 (RDat_P),
  .RDClk                (RDClk_P),
  .TCtl                 (TCtl_P),
  .TDat                 (TDat_P),
  .TDClk                (TDClk_P),
  .IdleRequest          (IdleRequest),
  .TrainingRequest      (TrainingRequest),
  .DataMaxT             (DataMaxT),
  .AlphaData            (AlphaData),
  .NumTrainSequences    (`DATA_NUM_TRAIN_SEQ),
  .SrcBurstLen          (SrcBurstLen),
  .SrcBurstMode         (SrcBurstMode),
  .SrcOof               (SrcOof),
  .SrcEn                (SrcEn),
  .SnkOof               (SnkOof),
  .SnkFFEmpty_n         (SnkFFEmpty_n),
  .SnkEn                (SnkEn),
  .TCComplete           (TCComplete),
  .SrcInFrame           (SrcInFrame)
);

/*****************************************************************************
* Instantiate status monitor (monitors Source & Sink status signals to
* verify they are behaving correctly)
*****************************************************************************/
pl4_lite_status_monitor pl4_lite_status_monitor0(
  .Reset_n              (Reset_n),
  .UserClk              (TSClkIn),
  .RStat                (RStat),
  .RSClk                (RSClk),
  .SnkOof               (SnkOof),
  .SnkAlmostFull_n      (SnkAlmostFull_n),
  .SnkDip2ErrRequest    (SnkDip2ErrRequest),
  .SrcOof               (SrcOof),
  .SrcDip2Err           (SrcDIP2Err),
  .TStat                (TStat),
  .TSClk                (TSClk),
  .SnkCalendar_Len      (SnkCalendar_Len),
  .SnkCalendar_M        (SnkCalendar_M),
  .FifoAFMode           (FifoAFMode),
  .CalWrEn_n            (SnkCalWrEn_n),
  .CalAddr              (SnkCalAddr),
  .CalData              (SnkCalData),
  .FullVec              (FullVec),
  .SnkInFrame           (SnkInFrame)
);

/*****************************************************************************
* Assign LVDS versions of SysClk
*****************************************************************************/
assign SysClk_P = SysClk;
assign SysClk_N = ~SysClk;

/*****************************************************************************
* Define constants for zero & one
*****************************************************************************/
initial
  begin
    zero_byte = 8'b0;
    zero      = 1'b0;
    one       = 1'b1;
  end

endmodule