pl4_lite_demo_testbench.v

spi接口的vhdl实现

/*****************************************************************************
* SPI-4.2 Looped Back Test Bench
******************************************************************************
*
*  Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
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*  grants you a license to use this text/file solely for
*  design, simulation, implementation and creation of
*  design files limited to Xilinx devices or technologies.
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*  prohibited and immediately terminates your license unless
*  covered by a separate agreement.
*
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*  All rights reserved.
*
******************************************************************************
* Filename: pl4_lite_demo_testbench.v
*
* Description: This file contains the top level of the PL4 testbench that
* loops back the FIFO side of the PL4 IP Core
*
****************************************************************************/
// Structure: pl4_lite_demo_testbench.v
//   |
//   +-- pl4_lite_stimulus.v
//   |      |
//   |      +-- pl4_lite_procedures.v
//   |
//   +-- pl4_lite_data_monitor.v
//   |
//   +-- pl4_lite_status_monitor.v
//   |
//   +-- pl4_lite_testcase.v
//   |      |
//   |      +-- pl4_lite_procedures.v
//   |
//   +-- pl4_lite_clk_gen.v
//   |
//   +-- pl4_lite_startup.v
//   |
//   +-- pl4_lite_wrapper.v
//          |
//          +-- pl4_lite_snk_top (post-ngdbuild gate-level simulation file)
//          |
//          +-- pl4_lite_src_top (post-ngdbuild gate-level simulation file)
//          |
//          +-- pl4_lite_fifo_loopback.v
//                      |
//                      +-- pl4_lite_fifo_loopback_read.v
//                      |
//                      +-- pl4_lite_fifo_loopback_write.v
//
//
/*****************************************************************************/

`timescale 1ps/1ps

/*****************************************************************************
* Library Declarations
*****************************************************************************/
`include "../pl4_lite_testcase_pkg.v"

/****************************************************************************
* Module Declarations
****************************************************************************/
module pl4_lite_demo_testbench();
wire    SysReset_n;
wire    Locked_RDClk;
wire    Locked_TDClk;

wire    DCMReset_TDClk;
wire    DCMReset_RDClk;
wire    SnkEn;
wire    SrcEn;
wire    SnkEnTC;
wire    SrcEnTC;
wire    SnkEnStartup;
wire    SrcEnStartup;
wire    SnkFifoReset_n;
wire    SrcFifoReset_n;

wire   [1:0]  TCStat;
wire   [15:0] TCChannel;
wire          TCCtl;
wire   [17:0] TCDat;
wire          TCIdleRequest;
wire          TCTrainingRequest;
wire          TCSnkDip2ErrRequest;
wire          CtlFull;
wire          FFWriteEn;
wire          SopErr;
wire   [7:0]  GetStatusChan;
wire   [1:0]  GetStatus;
wire          TCDIP2Request;
wire          RDClk_P;
wire          RDClk_N;
wire   [15:0] RDat_P;
wire   [15:0] RDat_N;
wire          RCtl_P;
wire          RCtl_N;
wire   [1:0]  RStat;
wire          RSClk;
wire   [1:0]  RStat_P;
wire   [1:0]  RStat_N;
wire          RSClk_P;
wire          RSClk_N;
wire          IdleRequest;
wire          TrainingRequest;
wire          SnkDip2ErrRequest;
wire    [1:0] TStat;
wire          TSClk;
wire    [1:0] TStat_P;
wire    [1:0] TStat_N;
wire          TSClk_P;
wire          TSClk_N;
wire          TSClkIn;
wire           SrcCalWrEn_n;
wire     [7:0] SrcCalData;
wire     [8:0] SrcCalAddr;
wire           SnkCalWrEn_n;
wire     [7:0] SnkCalData;
wire     [8:0] SnkCalAddr;
wire           SnkInFrame;
wire           SrcInFrame;
wire           SnkOof;
wire           SrcOofOverride;
wire           SrcOof;
wire   [255:0] FullVec;
wire           TDClk_P;
wire           TDClk_N;
wire           SnkBusErr;
wire    [7:0]  SnkBusErrStat;
wire           SnkTrainValid;
wire           SnkFFBurstErr;
wire           SnkAlmostFull_n;
wire           SnkOverflow_n;
wire           SnkFFEmpty_n;
wire    [7:0]  SnkCalDataOut;
wire           TCtl_P;
wire           TCtl_N;
wire    [15:0] TDat_P;
wire    [15:0] TDat_N;
wire    [7:0]  SrcCalDataOut;
wire           SrcDIP2Err;
wire           SrcStatFrameErr;
wire           SrcPatternErr;
wire           SnkClksRdy;
wire           SrcClksRdy;
wire    [7:0]  SnkCalendar_M;
wire    [8:0]  SnkCalendar_Len;
wire    [1:0]  FifoAFMode;
wire    [5:0]  SrcBurstLen;
wire           SrcBurstMode;
wire    [7:0]  SrcCalendar_M;
wire    [8:0]  SrcCalendar_Len;
wire    [15:0] DataMaxT;
wire    [7:0]  AlphaData;
wire 	       TCComplete;
reg     [8:0]  zero_byte;
reg            zero;
reg            one;


/*****************************************************************************
* Drive Static Configuration Signals
* Default values are defined in pl4_lite_testcase_pkg.vhd
*****************************************************************************/
assign SnkCalendar_M     = `SnkCalendar_M_default;
assign SnkCalendar_Len   = `SnkCalendar_Len_default;
assign FifoAFMode        = `FifoAFMode_default;
assign SrcBurstLen       = `SrcBurstLen_default;
assign SrcBurstMode      = `SrcBurstMode_default;
assign SrcCalendar_M     = `SrcCalendar_M_default;
assign SrcCalendar_Len   = `SrcCalendar_Len_default;
assign DataMaxT          = `DataMaxT_default;
assign AlphaData         = `AlphaData_default;

/*****************************************************************************
* Disable SrcOofOverride
*****************************************************************************/
assign SrcOofOverride    = 1'b0;

/*****************************************************************************
* Instantiate clock generator module
*****************************************************************************/
 pl4_lite_clk_gen # (
   .TDClkPeriod         (`TDCLK_PERIOD),
   .RDClkPeriod         (`RDCLK_PERIOD),
   .UserClkPeriod       (`USERCLK_PERIOD)
   )
pl4_lite_clk_gen0(
   .SysClk              (SysClk),
   .RDClk2x             (RDClk2x),
   .UserClk             (UserClk),
   .TSClk               (TSClkIn),
   .Reset_n             (Reset_n),
   .TDClk               (TDClk_P)
);

assign       SnkEn = SnkEnTC && SnkEnStartup;
assign       SrcEn = SrcEnTC && SrcEnStartup;

/*****************************************************************************
* Instantiate wrapper (contains sink & source cores and loopback module
*****************************************************************************/
pl4_lite_wrapper pl4_lite_wrapper0(
   .Reset_n            (Reset_n),
   .CalClk             (TSClkIn),
   .LoopbackClk        (UserClk),
   .RDClk_P            (RDClk_P),
   .RDClk_N            (RDClk_N),
   .RCtl_P             (RCtl_P),
   .RCtl_N             (RCtl_N),
   .RDat_P             (RDat_P),
   .RDat_N             (RDat_N),

   .RStat_P            (RStat_P),
   .RStat_N            (RStat_N),
   .RSClk_P            (RSClk_P),
   .RSClk_N            (RSClk_N),
   .SnkEn              (SnkEn),
   .SnkTriStateEn      (zero),
   .SnkFifoReset_n     (SnkFifoReset_n),

   .SnkOof             (SnkOof),
   .SnkBusErr          (SnkBusErr),
   .SnkFFBurstErr      (SnkFFBurstErr),
   .SnkFFDIP4Err       (),
   .SnkFFPayloadErr    (),
   .SnkFFPayloadDIP4   (),
   .SnkBusErrStat      (SnkBusErrStat),
   .SnkTrainValid      (SnkTrainValid),
   .SnkDIP2ErrRequest  (SnkDip2ErrRequest),

   .SnkAlmostFull_n    (SnkAlmostFull_n),
   .SnkOverflow_n      (SnkOverflow_n),
   .SnkFFEmpty_n       (SnkFFEmpty_n),